Deep Learning Accelerator Compiler for Cross-Platform ANN Instructions
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Solution Overview
Problem
Existing technologies face challenges in efficiently implementing Artificial Neural Networks (ANNs) on Deep Learning Accelerators due to energy consumption and computation time inefficiencies, particularly when dealing with large vector and matrix operations.
Innovation Solution
A compiler is developed to generate instructions executable by Deep Learning Accelerators, optimizing them for different hardware platforms by applying platform-agnostic optimization and further tailoring for specific accelerators, utilizing a combination of random access memory and specialized processing units to reduce energy consumption and computation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a compiler generates instructions for deep learning accelerators, then computation efficiency is improved, but device complexity increases
Solution Approach 1:
The compilation process is divided into distinct phases: a first phase that generates initial instructions based on the neural network description, and a second phase that optimizes these instructions for specific hardware platforms. This segmentation allows the compiler to handle complexity systematically, generating a baseline solution first, then applying targeted optimizations without overwhelming the entire compilation process.
Solution Approach 2:
The compiler performs preliminary optimization by generating instructions in a first phase before applying platform-specific optimizations in a second phase. This preliminary action establishes a solid foundation of computationally efficient instructions that can then be refined for specific hardware architectures, reducing the complexity of individual optimization steps.
2Use of energy by moving object
If platform-specific optimization is applied, then energy consumption is reduced, but compilation time increases
Solution Approach 1:
The compilation process is segmented into a first phase that generates general instructions and a second phase that applies platform-specific optimizations. This segmentation allows the compiler to perform heavy optimization computations only when necessary for specific hardware platforms, rather than continuously optimizing for all possible platforms, thus reducing overall compilation time while maintaining energy efficiency for target platforms.
Solution Approach 2:
The compiler applies full optimization only when needed for specific hardware platforms (partial action), rather than attempting to optimize for all possible platforms simultaneously. This approach reduces the total compilation time by skipping unnecessary optimization steps for platforms that don't require them, while still achieving energy efficiency for the platforms that do need optimization.
3Speed
If data access bottlenecks are reduced, then computation speed is improved, but device complexity increases
Solution Approach 1:
The compiler acts as an intermediary that translates high-level neural network operations into optimized low-level instructions tailored to the specific memory architecture of the target accelerator. This intermediary role allows the system to achieve fast data access without requiring complex changes to the hardware memory architecture itself, as the compiler optimizes data access patterns and memory operations to match the accelerator's capabilities.
Data Source
AI summary
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.