Deep Learning Accelerator Fault Tolerance via Neural Network Training

Solution Overview

Problem

Artificial neural networks (ANNs) in accelerators face challenges in tolerating random errors from compromised or corrupted memory cells, which can significantly affect the output of the network.

Innovation Solution

The integrated circuit device includes a deep learning accelerator (DLA) and random access memory (RAM) configured to store parameters and instructions for matrix computations. The DLA is trained to minimize the impact of random bit errors through machine learning techniques, allowing it to tolerate errors without relying on error correction code (ECC) computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction code (ECC) computations are used to tolerate random bit errors, then reliability is improved, but device complexity and computation time increase

Engineering Contradiction:

Improvefault toleranceVSAvoidcomputation complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary training of the neural network to make it inherently robust against random bit errors. By pre-adjusting the network parameters and structure during training, the system prepares the network to tolerate errors without requiring complex ECC computations during actual operation, thus resolving the contradiction between reliability and complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system converts the harmful effect of random bit errors into a beneficial training objective. By intentionally introducing random bit errors during training and using them to adjust network parameters, the system transforms error-prone memory operations into a mechanism for improving network robustness, eliminating the need for separate ECC mechanisms.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If error correction code (ECC) computations are used to tolerate random bit errors, then reliability is improved, but energy consumption increases

Engineering Contradiction:

Improvefault toleranceVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary training of the neural network to make it inherently robust against random bit errors. By pre-adjusting the network parameters and structure during training, the system prepares the network to tolerate errors without requiring complex ECC computations during actual operation, thus resolving the contradiction between reliability and complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system converts the harmful effect of random bit errors into a beneficial training objective. By intentionally introducing random bit errors during training and using them to adjust network parameters, the system transforms error-prone memory operations into a mechanism for improving network robustness, eliminating the need for separate ECC mechanisms.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If random bit errors occur in memory cells, then reliability deteriorates, but the system should maintain accurate output

Engineering Contradiction:

Improveoutput accuracyVSAvoidrandom bit errors

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The system converts the harmful effect of random bit errors into a beneficial training objective. By intentionally introducing random bit errors during training and using them to adjust network parameters, the system transforms error-prone memory operations into a mechanism for improving network robustness, eliminating the need for separate ECC mechanisms.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The system changes the parameters of the neural network through training to adapt to the presence of random bit errors. By adjusting weights, biases, and network architecture based on error-prone training data, the network learns to compensate for memory errors, maintaining output accuracy despite harmful factors.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250148275A1Fault tolerant artificial neural network computation in deep learning accelerator having integrated random access memory

Publication Date: 2025.05.08 MICRON TECHNOLOGY INC

AI summary

Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM) to store parameters of an artificial neural network (ANN). The device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the RAM accessed during computations of a first ANN output. A second ANN output is generated with the random bit errors applied to the data retrieved from the portion of the RAM. Based on a difference between the first and second ANN outputs, the device may adjust the ANN computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the RAM. For example, the sensitivity reduction may be performed through ANN training using machine learning.