Disc-Locked Clock Compensation for Patterned Media Misalignment

The patent introduces an intermediary compensation mechanism that measures the actual positions of timing fields and servo fields, calculates misalignment and eccentricity errors, and generates correction values to offset these errors. This intermediary system acts as a mediator between the imperfect multi-template manufacturing process and the required precise data storage operations, allowing high-density patterns to be used while maintaining positioning accuracy through real-time error compensation.

The patent implements a feedback-based compensation system where the actual positions of timing and servo fields are continuously measured, compared against ideal positions, and used to generate real-time correction values. The DLC circuit uses this feedback to dynamically adjust clock signals and counter initialization values, automatically compensating for misalignment errors without requiring complex mechanical adjustments or manual calibration procedures.

The patent segments the clock generation system into separate servo clock and data clock signal paths, each independently frequency-modulated based on their respective field position variations. This segmentation allows precise timing control for both servo and data operations simultaneously, while the modular structure of the DLC circuit manages the complexity by handling each clock type through dedicated but coordinated processing channels.

The patent applies preliminary action by pre-calculating and storing optimal counter initialization values that compensate for known precession errors at different radial positions on the BPM. Before data reading or writing operations commence, the system retrieves these pre-computed correction values and configures the counters accordingly, eliminating the need for complex real-time calculations during actual data operations and simplifying the counter management process.