DLD Metallization Structure With Short Vias for Lower Signal Resistance
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in reducing signal path resistance and improving conductivity between die interconnects and back end of line (BEOL) interconnect structures due to thick passivation layers that require polishing processes, which complicate fabrication and limit via height and width ratios.
Innovation Solution
A thinner passivation layer is used as a diffusion barrier between the die level distribution (DLD) metallization structure and the BEOL interconnect structure, minimizing the distance between them, and avoiding polishing steps to achieve shorter vias with aspect ratios between 0.06-0.5, thereby enhancing signal path conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick passivation layer is used to protect the metallization structure, then reliability is improved, but signal path resistance increases and manufacturing complexity increases due to polishing requirements
Solution Approach 1:
The patent changes the thickness parameter of the passivation layer from conventional thick (requiring polishing) to thin (0.5-2 micrometers), eliminating the need for polishing processes while maintaining adequate protection. This parameter change resolves the contradiction by achieving sufficient reliability without the manufacturing complexity of thick layer processing.
Solution Approach 2:
The patent extracts the polishing step from the fabrication process by using a thin passivation layer that does not require mechanical removal. This eliminates the complex polishing equipment and processes while maintaining the essential protective function, thereby reducing manufacturing complexity.
2Reliability
If a thick passivation layer is used, then diffusion barrier function is improved, but via aspect ratio is limited and signal path conductivity deteriorates
Solution Approach 1:
The patent changes the passivation layer thickness parameter to enable shorter vias with improved aspect ratios (0.06-0.5). This parameter change allows better via dimensional control and improved signal path conductivity while maintaining the diffusion barrier function through optimized thin layer materials and designs.
Solution Approach 2:
The patent applies local quality optimization by using thin passivation layers specifically in signal path regions where conductivity is critical, while maintaining adequate protection in other areas. This localized approach improves via aspect ratio control without compromising overall diffusion barrier functionality.
3Reliability
If a thick passivation layer is used, then protection is improved, but signal path resistance increases due to longer via length
Solution Approach 1:
The patent changes the passivation layer thickness parameter to reduce via length, thereby reducing signal path resistance. The optimized thin layer thickness (0.5-2 micrometers) maintains adequate protection while enabling shorter vias with lower resistance, resolving the contradiction between protection and conductivity.
Solution Approach 2:
The patent addresses the contradiction by optimizing the vertical dimension (thickness) of the passivation layer. By reducing thickness in the vertical dimension, via length is reduced, improving conductivity without sacrificing horizontal protection coverage, thus resolving the contradiction through dimensional optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process and significantly improves signal path conductivity by reducing resistance and increasing the surface area of vias, leading to higher conductivity without the need for polishing processes.
Implementation Method 1
a first passivation layer extending in the first direction adjacent to the outer metallization layer
Data Source
AI summary
Aspects disclosed in the detailed description include a semiconductor die having a die level distribution (DLD) metallization structure including a metal pad and a short via coupled to the metal pad to a metal interconnect in the die for improved signal path conductivity. The DLD metallization structure includes an outer metallization layer comprising the metal interconnect, a first passivation layer adjacent to the outer metallization layer and a DLD metallization layer adjacent to the first passivation layer. The DLD metallization layer comprises a first surface adjacent to the first passivation layer and a metal pad. The DLD metallization structure includes a first via extending in the second direction orthogonal to the first direction, the first via coupling the metal pad and the metal interconnect, the first via having a first aspect ratio between 0.06-0.5, inclusively.