D-LDO Clamp Strength Tuning for Ripple and Oscillation Control
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Solution Overview
Problem
Conventional Digital Low-drop Out (D-LDO) regulators face challenges with oscillations and output ripple noise due to variations in power device resistance and parasitic inductances, leading to inefficiencies and instability in voltage regulation, especially under dynamic load conditions.
Innovation Solution
A 3-level ripple quantization scheme with a power transistor strength-tuning mechanism that dynamically adjusts clamp strength based on ripple quantization patterns, eliminating oscillation risks and minimizing output ripple through asynchronous pulse patterns, without the need for current sensors or additional analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the D-LDO turns ON all devices to counter dynamic load changes, then the response speed to load transients is improved, but the output voltage experiences large overshoots and undershoots due to device resistance variations
Solution Approach 1:
The patent applies dynamics by making the clamp strength adjustable rather than fixed. The clamp strength is dynamically tuned based on detected oscillation patterns, allowing the system to adapt its response characteristics to match actual operating conditions and device variations, thereby achieving fast response without excessive overshoot
Solution Approach 2:
The patent implements feedback through an oscillation pattern detector that monitors the output voltage and provides information about oscillations back to the control logic. This feedback mechanism enables the system to detect and respond to oscillation conditions, adjusting the clamp strength to maintain stability while preserving fast transient response
2Stability of the object's composition
If the D-LDO uses fully ON devices to minimize droop, then the transient response is improved, but the output voltage exhibits sustained oscillations due to parasitic inductances
Solution Approach 1:
The patent converts the harmful effect of oscillations into useful information by detecting oscillation patterns. The detected oscillation information is then used to adjust the clamp strength, transforming the harmful oscillation phenomenon into a control signal that eliminates the oscillations while maintaining stable voltage regulation
Solution Approach 2:
The patent changes the clamp strength parameter based on detected oscillation patterns. By adjusting this key parameter dynamically, the system can suppress oscillations caused by parasitic inductances while maintaining the benefits of fully ON devices for minimizing droop and improving transient response
3Object-generated harmful factors
If the D-LDO increases clamp strength to reduce output ripple, then the ripple magnitude is reduced, but the system becomes more sensitive to oscillations from device variations
Solution Approach 1:
The patent makes the clamp strength dynamic rather than fixed, allowing it to be tuned based on detected oscillation patterns. This dynamic adjustment enables the system to reduce output ripple when conditions permit while increasing stability when oscillations are detected, resolving the trade-off between ripple reduction and stability
Data Source
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AI summary
A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.