DLL-Delayed Access Commands for Memory Clock Alignment
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Solution Overview
Problem
In memory devices, particularly three-dimensional cross-point and threshold-type memories, timing differences between the system clock domain and the data strobe or data clock domain can lead to challenges in aligning access commands, such as write commands, which can result in inefficient data transfer and storage operations.
Innovation Solution
The implementation of a delay locked loop (DLL) circuitry that aligns access commands with a reference clock signal, ensuring they undergo similar delays as data signals, thereby improving timing alignment between different clock domains and enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access commands are timed to the system clock domain, then clocking and latching of commands is achieved, but timing differences relative to the DQS domain occur
Solution Approach 1:
A delay locked loop (DLL) circuit is introduced as an intermediary component between the system clock domain and the DQS domain. The DLL receives the access command from the system clock domain, applies a calculated delay to it, and outputs the delayed command to the DQS domain. This intermediary structure allows timing synchronization between the two clock domains by compensating for the inherent timing differences through the delay mechanism.
2Productivity
If timing alignment between clock domains is achieved using DLL, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The delay locked loop employs a feedback mechanism where the timing relationship between the system clock and DQS signals is continuously monitored. The DLL adjusts its internal delay elements based on feedback about timing misalignment, automatically optimizing the command timing to maintain synchronization between clock domains. This feedback-based approach enables dynamic adaptation to timing variations while managing the complexity through automated control.
Data Source
AI summary
Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.