DLL Delay Line Activation Points for Lower Jitter Locking
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor ICs face limitations in area efficiency and increased internal jitter due to the length of the delay line, which affects operational stability and high integration and speed capabilities.
Innovation Solution
A DLL circuit with a delay line having two or more initial activation points, a delay compensating unit, a phase detecting unit, and a delay control unit that selectively adjusts the delay value based on the phase detection signal to optimize delay allocation, reducing the total delay amount to less than one cycle of the reference clock signal and minimizing internal jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line is initially set to a predetermined delay value (half of total delay amount), then the locking operation can proceed without interruption, but the total delay amount exceeds one cycle of the reference clock signal, increasing the delay line length
Solution Approach 1:
The delay line is divided into multiple sub-delay lines with different delay amounts. Instead of using a single long delay line, the invention segments the delay path into several shorter segments that can be selectively activated. This segmentation allows the delay line to achieve the required total delay without increasing the physical length of any single delay line segment, thereby reducing area occupation while maintaining reliable locking operation.
Solution Approach 2:
The invention dynamically selects and activates different initial activation points in the delay line based on the phase detection result. The delay control unit adjusts which sub-delay lines are activated during the locking operation, allowing the system to adaptively optimize the delay path. This dynamic adjustment enables the delay line to operate efficiently with reduced length while maintaining stability.
2Reliability
If the delay line length is increased to accommodate total delay exceeding one cycle, then the locking operation can be maintained, but internal jitter increases and area efficiency decreases
Solution Approach 1:
By segmenting the delay line into multiple sub-delay lines, the invention reduces the length of each individual delay path. This segmentation minimizes the accumulation of jitter along the delay path while maintaining the total delay required for locking operation. The shorter segmented paths generate less internal jitter compared to a single long delay line.
Solution Approach 2:
The phase detecting unit continuously monitors the phase difference between reference and feedback clock signals, and the delay control unit adjusts the activation of sub-delay lines based on this feedback. This feedback mechanism ensures that the locking operation remains stable and continuous while optimizing the delay path to minimize jitter generation.
3Ease of operation
If the delay line is configured with total delay of approximately two cycles, then the initial delay value can be set to half the total delay, but the delay line length increases, affecting area efficiency and operational stability
Solution Approach 1:
The delay line is segmented into multiple sub-delay lines with different delay amounts (e.g., first, second, third sub-delay lines with progressively smaller delays). This segmentation allows the system to achieve the required two-cycle total delay without increasing the physical area, as the sub-delay lines can be arranged more efficiently and share common circuitry.
Solution Approach 2:
Different portions of the delay line (sub-delay lines) have different delay characteristics optimized for their specific function. The first sub-delay line provides a larger initial delay, while subsequent sub-delay lines provide finer adjustment ranges. This local optimization allows efficient area utilization while maintaining ease of operation for delay value configuration.
4Device complexity
If a single delay line is used with fixed total delay amount, then the circuit structure is simple, but the delay line length increases and causes area inefficiency and increased jitter
Solution Approach 1:
Instead of a single fixed delay line, the invention uses multiple segmented sub-delay lines that can be selectively activated. While this increases structural complexity compared to a single delay line, it dramatically reduces the total area required and minimizes jitter. The segmented structure allows shared resources and more efficient layout, offsetting the increased complexity.
Solution Approach 2:
The multiple sub-delay lines serve multiple functions: they provide different delay amounts for various locking scenarios, enable dynamic adjustment of the delay path, and can be selectively activated based on phase detection results. This multi-functionality reduces the overall area requirement compared to having separate dedicated delay lines for each function.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.