DLL Delay Line Activation Points for Stable Locking
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Solution Overview
Problem
Conventional DLL circuits in semiconductor ICs face limitations in area efficiency and operational stability due to the length of the delay line, which increases internal jitter and hinders high integration and speed.
Innovation Solution
A DLL circuit with a delay line having multiple initial activation points and a configuration that allows selective activation based on phase detection signals, along with a semi-dual delay line structure, to adjust delay values efficiently and reduce the total delay amount to less than one cycle of the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line is initially set to a predetermined initial delay value (half of total delay amount), then the locking operation can be performed, but the total delay amount exceeds one cycle of the reference clock signal, causing the delay line length to increase
Solution Approach 1:
The patent applies preliminary action by setting the delay line to a minimum initial delay value at startup, and using a preliminary delay signal to temporarily extend the delay period. This allows the feedback clock signal to be generated at the correct phase even when the total delay would normally exceed one cycle, enabling successful locking without requiring a permanently longer delay line.
Solution Approach 2:
The patent introduces a preliminary delay signal as an intermediary element that temporarily adds delay to the feedback path during the initial locking phase. This intermediary allows the system to achieve proper phase alignment without permanently increasing the delay line length, resolving the contradiction between reliability and length.
2Reliability
If the delay line length is increased to accommodate total delay exceeding one cycle, then locking operation is enabled, but area efficiency decreases and internal jitter increases
Solution Approach 1:
The patent uses preliminary action by configuring the delay line to start at minimum length and temporarily extending the delay period through a preliminary delay signal during startup. This enables locking capability without permanently increasing the delay line area, thus resolving the contradiction between reliability and area efficiency.
3Reliability
If the delay line length is increased to accommodate total delay exceeding one cycle, then locking operation is enabled, but internal jitter increases and operational stability decreases
Solution Approach 1:
The patent applies preliminary action by using a temporary preliminary delay signal during the initial locking phase, allowing the system to achieve proper phase alignment without permanently increasing the delay line length. This maintains low jitter and high operational stability while enabling locking capability.
Solution Approach 2:
The patent implements dynamics by making the delay line configuration adaptive - starting at minimum length for low jitter, and temporarily extending delay period only when needed during startup. This dynamic approach maintains operational stability while enabling locking operation.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.