Delay-Locked Loop Anti-False Lock Circuit for Stable Strobe Timing
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) often experience false locks due to initial non-ideal delays, leading to harmonic or stuck locks, which result in incorrect strobe clock signals and operational instability.
Innovation Solution
Incorporating an anti-false lock (AFL) circuit that uses a phase detector, delay chain, and loop filter to detect and correct false lock states by adjusting the delay time of the output clock signal, preventing harmonic and stuck locks through a flexible detection range and operable range adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the initial delay time of the output clock signal is outside the range between 0.5 T to 1.5 T, then the DLL can operate with a wider delay range, but a false lock occurs resulting in incorrect strobe clock signals
Solution Approach 1:
The patent applies preliminary action by introducing an anti-false lock (AFL) circuit that performs preliminary detection of the delay time before the main locking operation. The AFL circuit compares the output clock signal with the reference clock signal in advance and generates a false lock detection signal if the delay time is outside the acceptable range, preventing incorrect locking before it occurs.
Solution Approach 2:
The patent implements feedback by using the false lock detection signal from the AFL circuit to continuously monitor and adjust the delay time. When a false lock condition is detected, the feedback mechanism adjusts the delay elements to bring the delay time within the 0.5 T to 1.5 T range, ensuring reliable locking while maintaining adaptability to different initial conditions.
2Device complexity
If a conventional DLL structure is used, then the device complexity is low, but false locks occur due to inability to detect initial non-ideal delays
Solution Approach 1:
The patent applies segmentation by dividing the locking function into two independent parts: the main phase detector for normal locking operation and the separate anti-false lock (AFL) circuit for false lock detection. This segmentation allows the AFL circuit to specifically monitor for false lock conditions without interfering with the main locking function, improving reliability while keeping each component relatively simple.
Solution Approach 2:
The patent introduces an intermediary element - the false lock detection signal - that mediates between the output clock signal and the locking control. This intermediary signal is generated by the AFL circuit when a false lock condition is detected and serves as a control input to prevent incorrect locking, adding reliability without requiring complete redesign of the DLL structure.
3Ease of operation
If the delay time is not precisely controlled, then the ease of operation is high, but incorrect strobe clock signals are generated leading to operational instability
Solution Approach 1:
The patent replaces manual or crude mechanical delay control with an automated electronic control system. The AFL circuit automatically detects false lock conditions and triggers adjustments to the delay elements through electronic control signals, eliminating the need for manual intervention while ensuring precise delay time control for accurate strobe clock generation.
Data Source
AI summary
A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.