Delay-Locked Loop Bandwidth Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Closed-loop clock circuits, such as phase-locked and delay-locked loops, face a trade-off between jitter and acquisition time, where reducing jitter increases acquisition time and vice versa, necessitating a solution to vary bandwidth based on phase error for improved performance.
Innovation Solution
A delay-locked loop with a variable loop bandwidth controlled by a filter, such as a moving-average or low-pass filter, whose depth and type are adjusted based on the phase error to optimize jitter and acquisition time, with an optional emulator circuit to compensate for delays in the feedback path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop bandwidth is increased, then acquisition time is reduced, but jitter is increased
Solution Approach 1:
The loop bandwidth is made dynamically adjustable rather than fixed. The system switches between a first loop bandwidth (higher) for acquisition mode and a second loop bandwidth (lower) for tracking mode, allowing optimization of both acquisition time and jitter performance at different operational stages
Solution Approach 2:
The patent changes the loop bandwidth parameter based on operational requirements. By transitioning from a higher bandwidth during acquisition to a lower bandwidth during tracking, the system optimizes performance metrics for each phase without compromising the other
2Manufacturing precision
If loop bandwidth is decreased, then jitter is reduced, but acquisition time is increased
Solution Approach 1:
The loop bandwidth transitions from a lower value during tracking to a higher value during acquisition. This dynamic adjustment allows the system to achieve low jitter during normal operation while maintaining fast acquisition capability when needed
Solution Approach 2:
The system changes the loop bandwidth parameter from low to high based on operational mode. During acquisition, the higher bandwidth enables fast locking, while during tracking, the lower bandwidth minimizes jitter for stable operation
3Productivity
If a fixed loop bandwidth is used, then circuit complexity is reduced, but performance optimization is limited
Solution Approach 1:
The system implements dynamic bandwidth adjustment with separate control modes (acquisition and tracking) to optimize performance for different operational requirements, accepting increased complexity for significant performance gains
Solution Approach 2:
The patent employs parameter changes in loop bandwidth based on operational phase, using control logic to switch between predefined bandwidth values, achieving performance optimization through structured parameter management
Data Source
AI summary
Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.