Delay-Locked Loop Bias Control for Stable High-Speed Clock Sync
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Solution Overview
Problem
Conventional delay-locked loop circuits become unstable due to rapid changes in UP/DN signals, leading to unsynchronized clock signals and chip instability at high-speed operations.
Innovation Solution
A delay-locked loop comprising a phase detector, shift register, digital low pass filter, digital-to-analog converter, and bias circuit, which generates lagging and leading signals, reduces signal frequency through grouping and converts them into bias voltages to stabilize the delay time, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the control voltage VCTL is used to control the delay line in conventional DLL, then the delay line can be adjusted to synchronize clocks, but the control voltage cannot keep up with rapid UP/DN signal changes causing instability
Solution Approach 1:
The patent segments the control voltage generation into multiple discrete voltage levels (e.g., 8 levels from 0.6V to 2.2V) corresponding to different delay amounts. Instead of using a continuous control voltage that changes rapidly, the system selects from predefined voltage levels, allowing the delay line to be adjusted in discrete steps that are easier to stabilize.
Solution Approach 2:
The patent implements a dynamic control mechanism where the control voltage is adjusted in discrete steps based on the phase detector output. The system dynamically selects appropriate voltage levels from a set of predefined levels, enabling the delay line to track phase differences while maintaining stability through controlled, step-wise adjustments rather than continuous rapid changes.
2Speed
If the operating frequency is increased to match improved semiconductor process, then the system performance improves, but clock skew and synchronization problems worsen
Solution Approach 1:
The patent employs a phase detector that continuously monitors the phase difference between the input clock and the delayed clock, providing feedback to the control logic. This feedback mechanism enables real-time adjustment of the delay line control voltage, ensuring that clock synchronization is maintained even at high operating frequencies where skew becomes more significant.
Solution Approach 2:
The patent changes the control parameter from continuous voltage to discrete voltage levels with specific delay amounts associated with each level. This parameter discretization allows for more predictable and controllable delay adjustments at high frequencies, improving synchronization reliability while maintaining high operating speeds.
3Device complexity
If a single capacitor loop filter is used in conventional DLL, then the circuit structure is simple, but the control voltage cannot respond quickly to signal changes causing instability
Solution Approach 1:
The patent extracts the filtering function from the traditional continuous voltage loop filter and replaces it with a digital control mechanism that selects from discrete voltage levels. This removes the need for a complex analog filter circuit while achieving better stability through the inherent smoothing effect of discrete level selection and capacitive charging/discharging in the delay line.
Data Source
AI summary
A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage.