Built-in Self-Test Circuit for Delay Locked Loop Timing Verification
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Solution Overview
Problem
Delay locked loop (DLL) circuits in memory controllers and other circuitry are difficult to troubleshoot due to intermittent timing issues caused by faulty DLLs, which can lead to system failures, necessitating a reliable testing method.
Innovation Solution
A built-in self-test (BIST) system utilizing two DLLs with a test controller to create a start offset and apply a common delay, allowing for the comparison of clock output signals to determine if the DLLs are functioning properly, identifying any changes that indicate a faulty DLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DLL circuits are used to maintain timing requirements in memory controllers, then timing precision is improved, but troubleshooting difficulty increases due to intermittent timing issues
Solution Approach 1:
The patent implements built-in self-test (BIST) circuitry that performs preliminary testing of DLL circuits during manufacturing and before deployment. The BIST circuitry proactively identifies faulty DLLs by comparing delay characteristics against reference values, preventing intermittent timing issues from occurring in the field and eliminating the need for complex troubleshooting of timing problems.
2Adaptability or versatility
If configurable DLLs are used to provide dynamic timing adjustments, then adaptability is improved, but reliability worsens due to increased complexity and potential for defects
Solution Approach 1:
The patent incorporates feedback mechanisms where the BIST circuitry continuously monitors the performance of configurable DLLs and compares their delay characteristics against reference values. When deviations are detected, the system can identify and isolate faulty DLLs, maintaining reliability while allowing configurable DLLs to provide dynamic timing adjustments for different memory modes and operating conditions.
3Adaptability or versatility
If multiple DLLs are used in memory controllers, then functional capability is improved, but testing complexity increases
Solution Approach 1:
The patent divides the testing function into modular BIST circuitry associated with each individual DLL. Each DLL has its own BIST circuit that can independently test and characterize delay values, allowing multiple DLLs to be tested separately and systematically. This segmentation reduces testing complexity by breaking down the overall testing task into manageable, repeatable units while maintaining the functional capability of using multiple DLLs for different memory timing requirements.
Data Source
AI summary
A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.