DLL Buffer Control for Stable Clock Locking Under Voltage Variation
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Solution Overview
Problem
DLL circuits in semiconductor integrated circuits face performance deterioration due to variations in DLL power supply voltage levels during power down and resume modes, leading to incorrect clock edge timing and locking reference point issues.
Innovation Solution
A DLL circuit with a buffer control unit that detects and compares the DLL power supply voltage to a reference level, enabling or disabling the buffer enable signal to stabilize clock delay locking operations, ensuring delay elements maintain pre-locked values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit operates during power down and resume modes, then the clock timing can be maintained continuously, but the voltage variations cause incorrect clock edge timing and locking reference point issues
Solution Approach 1:
The patent applies parameter changes by adjusting the reference level of the buffer control unit according to the operating mode (normal or power down). When voltage variations occur during power down mode, the reference level is adjusted to compensate for these variations, ensuring that the buffer enable signal is generated at the correct threshold despite the changing voltage conditions. This resolves the contradiction by changing the reference parameter dynamically to maintain reliable clock timing under varying voltage conditions.
2Duration of action of stationary object
If the buffer enable signal is continuously enabled to maintain clock operation, then clock continuity is improved, but power consumption increases and voltage variations cause timing errors
Solution Approach 1:
The patent applies dynamics by making the buffer control signal dynamic rather than static. The buffer control unit continuously monitors the voltage level and dynamically adjusts the buffer enable signal accordingly. During normal operation, the buffer operates normally; during power down mode with voltage variations, the reference level is adjusted dynamically to prevent incorrect timing while maintaining clock operation. This dynamic control optimizes both power consumption and clock continuity.
3Device complexity
If the reference level is fixed to ensure stable comparison, then comparison simplicity is maintained, but voltage variations cause incorrect buffer enable signal generation
Solution Approach 1:
The patent changes the reference level parameter based on the operating mode detected by the mode detection unit. Instead of using a fixed reference level, the system switches between different reference levels (normal mode reference level and power down mode reference level) depending on the current state. This parameter change approach maintains relatively simple control logic while significantly improving voltage comparison accuracy under varying operating conditions.
Data Source
AI summary
A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.