DLL Buffer Shutdown Timing for Stable Power-Down Recovery
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Solution Overview
Problem
Conventional DLL circuits in synchronous memory devices consume excessive power during power-down mode due to the need to maintain buffer 112 enabled, leading to incorrect phase detection and prolonged locking times upon exiting power-down mode.
Innovation Solution
A DLL circuit design that disables both clock buffers during power-down mode and uses a controller to synchronize the phase comparator's enablement with the delay time of the second delay line and replica delay unit, preventing premature operation and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If buffer 112 is disabled during power-down mode to reduce power consumption, then power consumption is reduced, but the phase comparator receives incorrect signals causing wrong phase detection and prolonged locking time
Solution Approach 1:
The patent applies preliminary action by enabling the phase comparator before disabling buffer 112 during power-down mode. Specifically, the phase comparator is enabled at a first timing while buffer 112 is still in the enable state, allowing it to receive and process valid clock signals. This preliminary enablement ensures that when buffer 112 is subsequently disabled to save power, the phase comparator has already been prepared and will not suffer from signal loss, thus maintaining phase detection accuracy while achieving power savings.
2Reliability
If buffer 112 is kept enabled during power-down mode to maintain correct phase detection, then phase detection accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by enabling the phase comparator before disabling buffer 112 during power-down mode. Specifically, the phase comparator is enabled at a first timing while buffer 112 is still in the enable state, allowing it to receive and process valid clock signals. This preliminary enablement ensures that when buffer 112 is subsequently disabled to save power, the phase comparator has already been prepared and will not suffer from signal loss, thus maintaining phase detection accuracy while achieving power savings.
3Productivity
If buffer 112 is enabled upon exiting power-down mode, then the DLL circuit can operate, but the phase comparator makes wrong decisions due to delayed feedback signal causing prolonged locking time
Solution Approach 1:
The patent applies preliminary action by enabling the phase comparator at a first timing before buffer 112 is disabled during power-down mode, and maintaining it in the enable state throughout the power-down period. When exiting power-down mode, buffer 112 is re-enabled at a second timing while the phase comparator remains enabled, allowing it to immediately receive valid clock signals and perform correct phase detection without delay. This preliminary and sustained enablement of the phase comparator eliminates wrong decisions and reduces locking time, thereby improving DLL operation speed.
Data Source
AI summary
A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.