Delay Locked Loop Calibration Without Extra Reference Clocks
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Solution Overview
Problem
Current methods for calibrating delay locked loops (DLLs) in semiconductor memory devices require routing additional reference clocks, which is resource-intensive and costly, and do not efficiently account for process, voltage, and temperature (PVT) variations, leading to potential read and write errors.
Innovation Solution
A method for calibrating a DLL by determining segment delay values, calculating full-cycle delay values, adjusting segment delay values, and calculating weights for the delay segments to generate precise phase delays without the need for additional reference clocks, using a minimal number of components and quickly meeting timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional reference clocks are routed to all DLLs for calibration, then calibration precision is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent extracts the calibration function from the traditional multi-reference-clock approach and implements it using a single reference clock combined with a phase detector and delay elements. This eliminates the need for routing multiple reference clocks to each DLL, reducing routing complexity while maintaining calibration precision through the phase detection mechanism.
Solution Approach 2:
The single reference clock is made universal by using it for both normal operation and calibration purposes. The phase detector and delay elements enable this single clock to serve multiple functions: providing the reference signal for DLL operation and simultaneously enabling precision calibration through phase comparison, thereby eliminating the need for separate calibration reference clocks.
2Measurement precision
If multiple reference phases are generated for DLL calibration, then calibration accuracy is improved, but manufacturing cost and routing restrictions increase
Solution Approach 1:
The patent segments the calibration function into discrete delay elements that can be individually adjusted. Instead of generating multiple reference phases, the system uses a single reference clock and divides the calibration task into multiple small delay steps, each controlled by individual delay elements. This segmentation allows precise calibration without the manufacturing complexity of generating multiple reference phases.
Solution Approach 2:
The patent introduces dynamic adjustability through controllable delay elements that can be tuned during calibration. Rather than relying on static multiple reference phases, the system dynamically adjusts the delay of individual elements based on phase detector feedback, enabling accurate calibration without the need for multiple fixed reference clock phases.
3Reliability
If traditional calibration methods are used with multiple reference clocks, then DLL timing requirements are met, but resource usage and system expansion become problematic
Solution Approach 1:
The patent merges the calibration function with the normal DLL operation by using the same reference clock for both purposes. The phase detector and delay elements are integrated into the existing DLL structure, combining calibration and operation functions into a single unified system. This eliminates the need for separate calibration resources while maintaining timing requirements.
Solution Approach 2:
The DLL system performs self-calibration using its own reference clock and internal phase detector, without requiring external calibration resources. The phase detector compares the DLL output with the reference clock and automatically adjusts the delay elements to achieve proper timing, enabling the system to calibrate itself using minimal internal resources.
Data Source
AI summary
A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.