Delay-Locked Loop Calibration for Safe VCDL Control Voltage
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Solution Overview
Problem
Existing delay locked loop (DLL) circuits face challenges in maintaining accurate phase alignment due to limitations in the range of acceptable control voltages, leading to incorrect phase locking when the control voltage exceeds safe limits.
Innovation Solution
The proposed DLL circuit incorporates a voltage-controlled delay line (VCDL) calibrated to maintain the control voltage within a safe range by sequentially applying candidate delay codes until the last output signal is 2Π radians out of phase with the first output signal, ensuring accurate phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the control voltage range is extended to accommodate PVT variations, then the adaptability improves, but the phase alignment accuracy deteriorates due to incorrect phase locking
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal operation. The calibration mode pre-determines the relationship between delay codes and actual delay values under specific PVT conditions, storing this calibration data for use during normal operation. This preliminary calibration ensures that when the DLL operates in normal mode, it can accurately compensate for PVT variations without extending the control voltage range, thus maintaining phase alignment accuracy while adapting to different conditions.
Solution Approach 2:
The patent utilizes parameter changes by varying the delay code parameters during calibration to establish a mapping between delay codes and actual delay values. By changing the delay code parameters systematically during calibration and storing the results, the system can later select appropriate delay codes based on measured PVT conditions, achieving adaptability without compromising phase alignment accuracy through control voltage extension.
2Manufacturing precision
If a calibration mode is added to calibrate the delay line, then the phase alignment accuracy improves, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing the calibration mode to share common circuit components with the normal operation mode. The same voltage-controlled delay line, phase detector, and counter are used in both calibration and normal modes. The calibration mode simply adds control logic to sequentially apply delay codes and store calibration data, rather than requiring separate dedicated calibration hardware. This multi-functional design achieves accurate phase alignment calibration while minimizing the increase in device complexity.
3Reliability
If the control voltage is limited to a safe range, then the reliability improves, but the ability to compensate for large PVT variations deteriorates
Solution Approach 1:
The patent introduces an intermediary approach by using delay codes as a discrete parameter to control the delay line instead of relying solely on continuous control voltage adjustments. The calibration process establishes a mapping between discrete delay codes and actual delay values, allowing the system to select appropriate delay codes based on measured PVT conditions. This intermediary use of delay codes enables the system to achieve both reliability (by keeping control voltage within safe ranges) and adaptability (by selecting from multiple calibrated delay code options to compensate for various PVT variations).
Data Source
AI summary
A delay locked loop circuit comprising: a voltage-controlled delay line (VCDL); a phase detector circuit that is configured to process a first and a last output signal of the VCDL in order to provide: i) an up-pulse signal; and ii) a down-phase signal; a charge pump that is configured to provide a feedback voltage signal based on the up-pulse signal and the down-pulse signal; a phase signal processor that is configured to process the up-pulse signal and the down-pulse signal in order to provide a delay code locking signal, which is representative of whether or not the first output signal is 2Π radians out of phase with the last output signal; a delay code setter that is configured to provide a delay code setting signal that represents one of a sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration mode of operation: a fixed voltage source provides a fixed voltage signal as a control-voltage signal for the voltage-controlled delay line; while the delay code locking signal represents the first output signal not being 2Π radians out of phase with the last output signal: the delay code setter applies the delay code setting signal to the VCDL such that it sequentially applies different candidate delay codes to the voltage-controlled delay line until a selected-delay-code is assigned; and when the delay locked loop circuit is in the active mode of operation: a charge pump provides a feedback voltage signal as the control-voltage signal for the voltage-controlled delay line; and the VCDL uses the selected-delay-code as the delay code.