DLL Duty Cycle Correction Through Capacitor Voltage Delay Tuning
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Solution Overview
Problem
Existing digital duty cycle correction circuits for DDR SDRAM face challenges in achieving high-speed operation while minimizing power consumption and area, with analog DCC being accurate but difficult to implement at high speeds and digital DCC occupying large area and consuming high power.
Innovation Solution
A digital duty cycle correction circuit that controls delay within a DLL by varying the voltage applied to capacitors, using a phase divider, compare control unit, DCC pump, voltage comparator, counter, and voltage generator to correct the duty cycle of an output clock, allowing for efficient high-speed operation with reduced power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog DCC circuit is used for duty cycle correction, then correction accuracy is improved, but implementation difficulty increases at high-speed operation
Solution Approach 1:
The patent replaces the analog DCC circuit (electronic/mechanical system) with a digital DCC circuit implemented in logic gates and flip-flops. This substitution enables duty cycle correction to be achieved through digital logic operations rather than analog voltage/current manipulation, making the circuit easier to implement at high speeds while maintaining correction accuracy.
Solution Approach 2:
The patent changes the operating parameters of the DCC circuit by using digital voltage levels (0V and VDD) instead of continuous analog voltages. The delay control is achieved by adjusting the number of clock cycles in a digital counter rather than adjusting analog time constants, enabling precise duty cycle correction at high operating frequencies.
2Productivity
If a digital DCC circuit is used for duty cycle correction, then ease of high-speed operation is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent segments the DCC function into modular digital components: a phase detector that identifies duty cycle errors, a counter that generates correction pulses, and logic gates that implement the correction. This segmentation allows for efficient resource utilization and reduces the overall circuit area compared to a monolithic digital DCC implementation.
Solution Approach 2:
The patent uses a simplified digital model of the delay mechanism using counter-based pulse generation instead of complex digital delay lines. This copying approach replicates the essential delay function using fewer logic elements, reducing circuit area while maintaining high-speed operation capability.
3Productivity
If a digital DCC circuit is used for duty cycle correction, then ease of high-speed operation is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using clocked flip-flops and counters that operate only on clock edges. The DCC circuit processes duty cycle correction in periodic cycles synchronized with the system clock, enabling high-speed operation while minimizing power consumption by keeping circuit elements in a low-power state between clock cycles.
Solution Approach 2:
The patent employs self-service by using the existing system clock and existing logic resources (phase detectors, counters) that are already present in the DDR SDRAM architecture. The DCC function leverages these existing components rather than requiring dedicated high-power circuitry, reducing overall power consumption while achieving high-speed correction.
Data Source
AI summary
The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.