Dynamically Biased DLL Charge Pump for Low-Jitter Delay Control
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Solution Overview
Problem
Delay-Locked Loops (DLLs) face issues with jitter, duty cycle distortion, and static phase offset due to large delays, which are undesirable in various applications such as frequency-multiplying and deskew operations.
Innovation Solution
The implementation of a master/slave DLL system with a charge pump and phase detector that adjusts delay lines to minimize jitter and static phase offset by using a feedback loop to control the delay elements, ensuring precise alignment of signal edges through a regulated supply voltage and dynamic self-biasing of the charge pump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If large delays are implemented in the delay line to achieve significant signal delay, then the delay capability is improved, but jitter increases proportionally
Solution Approach 1:
The delay line is divided into multiple delay elements (first delay element, second delay element, etc.) that can be independently controlled. Each element contributes a portion of the total delay, allowing the system to achieve large overall delay while maintaining better control over jitter in each segment. The phase detector compares edges from different segments and the charge pump adjusts bias currents for each element separately to minimize cumulative jitter.
Solution Approach 2:
The invention dynamically adjusts the bias current parameters of individual delay elements based on phase detection results. By changing the bias current parameters of each delay element independently, the system can optimize the delay characteristics and minimize jitter while maintaining the required large overall delay. The charge pump modifies these parameters in response to phase error signals from the phase detector.
2Loss of time
If large delays are implemented in the delay line to achieve significant signal delay, then the delay capability is improved, but duty cycle distortion increases
Solution Approach 1:
Different delay elements are provided with different bias currents to compensate for local variations in propagation characteristics. The first delay element receives a first bias current while the second delay element receives a second bias current, allowing each element to be optimized for its specific position in the delay line. This local optimization reduces cumulative duty cycle distortion while maintaining the required large overall delay.
Solution Approach 2:
The bias current parameters are dynamically adjusted based on duty cycle detection. The system monitors the duty cycle at the output and modifies the bias currents of individual delay elements to correct distortions. By changing these parameters in response to measured duty cycle errors, the system maintains accurate pulse width despite implementing large delays.
3Device complexity
If conventional charge pump biasing is used to control delay elements, then the device complexity is reduced, but static phase offset and jitter increase
Solution Approach 1:
A phase detector is implemented to continuously monitor the phase relationship between the delayed signal edge and the reference clock edge. The phase detector generates a feedback signal that is processed by the charge pump to adjust the bias currents of the delay elements. This feedback mechanism eliminates static phase offset by continuously correcting any phase errors and reduces jitter by dynamically optimizing the delay characteristics based on real-time phase measurements.
Solution Approach 2:
The charge pump automatically adjusts its own bias currents based on feedback from the phase detector without requiring external intervention. The system self-regulates by using the phase error signal to modify the bias currents of the delay elements, thereby eliminating static phase offset and minimizing jitter autonomously. The DLL circuit serves itself by using its own output to control its own operation.
Data Source
AI summary
A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.