DLL Phase Detector Charge Pump for Low-Power Phase Shifting
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Solution Overview
Problem
Existing delay-locked loops (DLLs) face challenges in reducing power consumption while maintaining precise phase shifting, especially as clock frequencies increase in memory systems.
Innovation Solution
The implementation of a charge pump with active and inactive logic levels in a DLL, utilizing a phase detector that generates charge up and charge down control signals based on the phase difference between reference and feedback clock signals, and a loop filter with a capacitor to provide a variable bias voltage for the voltage-controlled delay line, allowing for efficient charging and discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional charge pump circuits are used in DLLs, then phase shifting functionality is maintained, but power consumption increases
Solution Approach 1:
The charge pump circuit operates periodically by enabling the charge pump only during specific phases when phase adjustment is needed, rather than continuously operating. The control logic detects phase differences and activates the charge pump transiently to correct phase errors, then disables it when locked, significantly reducing average power consumption while maintaining phase shifting precision.
Solution Approach 2:
The patent implements different operational modes for different parts of the phase detector circuit. The first phase detector portion operates continuously to detect phase differences, while the charge pump is activated only locally and temporarily when correction is needed. This localized activation reduces overall power consumption while maintaining the reliability of phase shifting functionality.
2Speed
If clock frequency is increased in memory systems, then data transmission speed is improved, but power consumption and phase shifting precision become more difficult to maintain
Solution Approach 1:
The DLL circuit dynamically adapts its operation to match the clock frequency. The phase detector continuously monitors phase differences at the current operating frequency, and the charge pump dynamically adjusts delay elements in real-time to maintain proper phase relationships. This dynamic adaptation allows the system to operate reliably at high frequencies while consuming power only when adjustments are needed, rather than continuously.
Solution Approach 2:
The system employs feedback mechanisms where the phase detector continuously monitors the phase relationship between reference and feedback clock signals. Based on this feedback, the control logic activates the charge pump only when phase errors are detected, allowing the DLL to automatically compensate for frequency variations and maintain precision at high clock rates without excessive power consumption.
3Reliability
If continuous operation of charge pump is used, then phase locking is maintained, but power consumption increases
Solution Approach 1:
The charge pump operates periodically rather than continuously. The control logic monitors phase detection outputs and activates the charge pump only during periods when phase correction is needed. Once phase locking is achieved, the charge pump is disabled or operated at reduced duty cycle, maintaining phase lock through the memory effect of the delay line while dramatically reducing power consumption during steady-state operation.
Solution Approach 2:
The DLL circuit uses its own phase detection output to control the charge pump operation. When phase locking is achieved, the circuit self-regulates by reducing charge pump activity, using the stored state in the delay line elements to maintain locking without continuous active correction, thereby reducing power consumption while maintaining reliability.
Data Source
AI summary
The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.