Self-Biased DLL Circuit for DC-DC Converter Frequency-Proportional Bias
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Solution Overview
Problem
DC-DC converters face inefficiencies at low load currents due to high quiescent current draw during pulse frequency modulation (PFM) operation, which can lead to inadequate bandwidth and increased power losses, as existing techniques struggle to adjust bias current levels effectively with varying pause periods across multiple decades of frequency.
Innovation Solution
A self-biased delay lock loop (DLL) circuit generates a frequency-proportional bias current signal to adjust quiescent current levels in DC-DC converter controller circuits, ensuring adequate bandwidth and reduced power draw by locking onto the PFM repetition rate, utilizing a monostable multivibrator, phase detector, and charge pump circuitry to provide a bias current signal inversely proportional to PFM pause duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If quiescent current is reduced to improve power efficiency during PFM pauses, then power loss decreases, but bandwidth and wake-up time of control circuits deteriorate
Solution Approach 1:
The bias current is made dynamic rather than static, automatically adjusting its magnitude based on the PFM repetition frequency. During heavy loading when PFM frequency is high, the bias current increases to maintain adequate bandwidth and response time. During light loading when PFM frequency is low, the bias current decreases to minimize power consumption. This dynamic adaptation resolves the contradiction between power efficiency and bandwidth by making the bias current proportional to the actual operating conditions.
Solution Approach 2:
The circuit employs feedback mechanisms where the PFM repetition frequency serves as a feedback signal to control the bias current magnitude. The control circuit monitors the switching activity and adjusts the bias current accordingly, creating a closed-loop system that automatically optimizes the trade-off between power consumption and performance based on real-time operating conditions.
2Reliability
If fixed bias current is used to maintain adequate bandwidth, then response time is sufficient, but power consumption increases during low load currents
Solution Approach 1:
The bias current transitions from a fixed value to a dynamic value that varies with PFM repetition frequency. This allows the system to maintain high bias current (and thus adequate response time) only when necessary during heavy loading, while reducing bias current during light loading to minimize power consumption, directly resolving the contradiction between response time and power consumption.
Solution Approach 2:
The magnitude of the bias current parameter is changed dynamically based on the PFM repetition frequency. By making this parameter variable rather than constant, the system can optimize power consumption at each operating point while maintaining sufficient response time when required, eliminating the need for a fixed high bias current that wastes power during light loading.
3Loss of energy
If PFM pause period varies across multiple decades to adapt to different load conditions, then efficiency improves, but it becomes difficult to set appropriate quiescent current levels
Solution Approach 1:
The control circuit automatically determines the appropriate bias current level based on the actual PFM repetition frequency without requiring external intervention or manual configuration. The circuit serves itself by using its own operating parameters (PFM frequency) to control its bias conditions, eliminating the complexity of external current setting while maintaining optimal efficiency across all load conditions.
Solution Approach 2:
The bias current parameter is made variable and automatically adjusted according to PFM repetition frequency, allowing the system to adapt to different load conditions and pause periods without requiring complex external configuration. This parameter change approach simplifies the overall system by eliminating manual current setting while optimizing efficiency across multiple decades of operating conditions.
Data Source
AI summary
Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.