Delay-Locked Loop Clock Alignment for Low Jitter Data Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loop (DLL) circuits face challenges in accurately generating clock signals with varying phases due to increased clock frequencies, leading to clock skew and phase jitter issues during data transmission, which are not effectively addressed by existing multi-phase clock generating circuits.
Innovation Solution
A DLL circuit configuration comprising multiple DLL sections and an input signal delay section, utilizing differential and single signal converting circuits, phase comparing circuits, and digital control delay circuits to generate and control phase delayed signals, ensuring precise phase alignment and minimizing phase jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to operate circuit blocks at higher speed, then productivity is improved, but clock skew and phase jitter occur causing transmission errors
Solution Approach 1:
The patent implements dynamic delay adjustment in the delay circuit by using a delay control signal that can be adjusted based on feedback from the phase comparator. This allows the delay circuit to adaptively compensate for phase variations caused by high clock frequencies, maintaining synchronization between transmission and reception sides while operating at higher speeds.
Solution Approach 2:
The patent employs a feedback mechanism where the phase comparator compares the phase of the delayed clock signal with the reference clock signal and generates a phase difference signal. This feedback signal is used to adjust the delay control signal, creating a closed-loop system that automatically corrects phase skew and jitter, thereby ensuring reliable data transmission at high frequencies.
2Reliability
If phase relationship is made different between transmission and reception sides to avoid clock skew, then reliability is improved, but device complexity increases due to multiple control circuits
Solution Approach 1:
The patent combines the delay control function with the existing phase-locked loop structure. The delay control signal is generated within the PLL framework by utilizing the phase difference signal from the phase comparator, thereby integrating multiple functions (phase detection, delay adjustment, and synchronization) into a unified control mechanism rather than requiring separate independent control circuits.
Solution Approach 2:
The phase comparator serves multiple functions: it detects phase differences between clock signals, generates control signals for delay adjustment, and maintains synchronization between transmission and reception sides. This multi-functional approach reduces the need for dedicated separate circuits for each function, simplifying the overall system architecture.
3Measurement precision
If delay time is controlled to have predetermined delay time, then measurement precision is improved, but device complexity increases due to slave DLL circuit
Solution Approach 1:
The delay circuit automatically adjusts its delay time based on the phase difference signal from the phase comparator without requiring external intervention or complex master-slave control architecture. The system self-regulates by using the phase error signal to control the delay element, achieving precise delay control through self-service mechanisms within the PLL structure.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay. A second DLL section delays the reference clock signal in response to a second control signal, and generates the second control signal based on the reference clock signal delayed in the second DLL section and the phase delayed signal. An input signal delay section delays an input signal in response to the second control signal.