DLL Multiphase Clock Generator With Anti-Harmonic Lock Control
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Solution Overview
Problem
Conventional delay-locked loop-based multiphase clock generators face issues with harmonic lock and incorrect output frequencies due to layout and delay mismatches in voltage controlled delay lines, and suffer from increased power source voltage noises caused by sudden changes in operation frequency.
Innovation Solution
A delay-locked loop-based multiphase clock generator is developed, incorporating an anti-harmonic lock circuit to prevent harmonic lock and calibrate delay mismatches, and a dithering circuit to suppress power source voltage noises, using a voltage controlled delay line with dummy cells and a frequency multiplier to generate stable multiphase clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional delay-locked loop-based multiphase clock generators use a plurality of multiphase clocks output from a voltage controlled delay line, then high speed clock generation is achieved, but harmonic lock occurs and output frequencies may not be correctly generated due to layout mismatch and delay mismatch
Solution Approach 1:
The patent applies preliminary action by performing delay calibration before normal clock generation operation. The calibration mode pre-adjusts the delay cells to compensate for layout mismatches and delay variations, ensuring accurate output frequencies when switching to normal mode. This preliminary calibration step prevents harmonic lock and frequency errors before they occur during high-speed operation.
Solution Approach 2:
The patent changes the operational parameters of the delay-locked loop by switching between calibration mode and normal mode. During calibration mode, the delay cell parameters are adjusted to achieve precise timing alignment. This parameter change approach allows the system to maintain both high speed performance and frequency accuracy by optimizing delay characteristics under different operating conditions.
2Adaptability or versatility
If current flowing through a conductive line is suddenly changed due to a sudden change of an operation frequency, then frequency switching is achieved, but power source voltage noises are increased which may result in deterioration of performance
Solution Approach 1:
The patent applies periodic action through the dithering circuit that periodically switches between adjacent frequency channels during frequency transitions. Instead of making sudden frequency changes, the system performs periodic switching between current and next frequency channels, which distributes the current change over time and reduces peak noise levels. This periodic transition approach maintains frequency switching capability while minimizing power source voltage noise.
3Measurement precision
If an anti-harmonic lock block is added to prevent harmonic lock and calibrate delay mismatches, then output frequency accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration functionality into the existing delay-locked loop structure by integrating calibration mode with normal operation mode. The same delay cells and control logic are used for both calibration and normal clock generation, eliminating the need for separate calibration hardware. This merging approach improves output frequency accuracy while minimizing the increase in device complexity.
4Reliability
If a dithering circuit is added to suppress power source voltage noises, then circuit performance is maintained, but device complexity increases
Solution Approach 1:
The dithering circuit is designed to automatically activate and deactivate based on frequency transition detection, without requiring external control signals. The circuit self-manages the frequency switching process by detecting frequency change conditions and autonomously performing the periodic switching between adjacent channels. This self-service capability maintains circuit performance stability while minimizing the increase in device complexity by eliminating the need for additional control logic.
Data Source
AI summary
The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range.