DLL Clock Buffer Control for Low-Power Memory Precharge
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Solution Overview
Problem
Conventional semiconductor memory devices face high current consumption during the precharge power-down mode due to the need to maintain the second clock buffer active, which compromises operation reliability and delays the achievement of the delay locking state.
Innovation Solution
A delay locked loop (DLL) with a clock buffer controller that generates a clock buffer enable signal based on precharge power-down mode and reset signals, allowing for controlled buffering and feedback loop operation to minimize current consumption while ensuring delay locking state maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second clock buffer is kept active during precharge power-down mode to maintain delay locking state, then operation reliability is improved, but current consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock buffer's operational state changeable based on timing conditions. The second clock buffer is dynamically controlled to be deactivated after a predetermined time period following an activate command, transitioning from an always-active state to a conditionally-active state, thereby reducing power consumption while maintaining reliability during critical periods
Solution Approach 2:
The patent implements periodic action by deactivating the second clock buffer after a predetermined time period following an activate command. This periodic deactivation creates intervals of low power consumption while ensuring the delay locking state is maintained during critical operation periods, achieving a balance between reliability and energy efficiency
2Use of energy by moving object
If the second clock buffer is deactivated during precharge power-down mode to reduce current consumption, then energy efficiency is improved, but the delay locking state may not be achieved timely causing malfunctions
Solution Approach 1:
The patent applies preliminary action by keeping the second clock buffer active for a predetermined time period after an activate command before deactivating it. This preliminary active period ensures the delay locking state is established and maintained during critical operations, preventing malfunctions while enabling subsequent power savings
Solution Approach 2:
The patent implements feedback by using the timing of activate commands and the predetermined time period to control the deactivation of the second clock buffer. This feedback mechanism ensures the buffer remains active during critical periods when delay locking is needed, and is deactivated during safe periods, balancing power consumption with operational reliability
Data Source
AI summary
A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.