DLL Clock Buffer Timing for Stable SDRAM Power-Down Transitions
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Solution Overview
Problem
Conventional DLL circuits in semiconductor memory devices face issues where phase updates can be interrupted or conducted with wrong information when transitioning from normal to power-down mode, leading to instability in clock synchronization.
Innovation Solution
A DLL circuit design that includes a power-down mode controller and clock buffer controller, which generates control signals to halt phase updates and delay the clock buffer off-time until a final signal indicates the end of the phase update period, ensuring accurate phase update completion before entering power-down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock buffer is turned off immediately when entering power-down mode, then power consumption is reduced, but phase update operations are interrupted causing clock synchronization instability
Solution Approach 1:
The patent applies preliminary action by detecting the power-down mode entry beforehand and delaying the clock buffer shutdown until after the phase update operation completes. The control unit monitors the phase update status and only turns off the clock buffer when the update is finished, preventing interruption while still achieving power savings.
2Measurement precision
If phase update operations continue during power-down mode entry, then clock synchronization accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock buffer operation dynamic rather than static. The buffer remains active only during the critical phase update period and is turned off afterward. The control unit dynamically adjusts the buffer state based on real-time phase update completion status, optimizing both accuracy and power consumption.
3Measurement precision
If the clock buffer shutdown is delayed until phase update completion, then phase update accuracy is ensured, but transition time to power-down mode increases
Solution Approach 1:
The patent applies feedback by implementing a control unit that continuously monitors phase update completion status and uses this feedback to control the clock buffer shutdown timing. The system waits for confirmation that the phase update is complete before turning off the buffer, ensuring accuracy while minimizing unnecessary delays.
Data Source
AI summary
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The present invention can prevent a phase update operation from being interrupted when the DLL circuit enters a power-down mode. For the above purpose, an off operation of a clock buffer is delayed until a clock signal notifying a final period of the phase update is activated.