Delay Locked Loop Clock Cycle Sensing for Low-Jitter Phase Sync
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Solution Overview
Problem
In semiconductor devices, the internal clock phase often becomes asynchronous with the external clock due to buffering through internal circuits, leading to potential data desynchronization, and existing delay locked loop (DLL) circuits face limitations in adjusting delay amounts, which can result in operation failures or increased jitter.
Innovation Solution
A semiconductor device circuit that includes a delay line, a delay amount sensing unit, a clock cycle measuring unit, and a delay amount controlling unit to logically adjust the delay amount by one cycle of the source clock, allowing for dynamic change in delay units without physical size constraints, thereby preventing operation failures and minimizing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the delay amount of the delay line is fixed at a minimum physical value, then the circuit area is minimized, but the DLL circuit cannot achieve proper phase synchronization when larger delay is needed
Solution Approach 1:
The patent implements dynamic delay adjustment by introducing a delay amount controlling unit that can dynamically change the delay amount of the delay line based on control signals. This allows the DLL circuit to adaptively adjust delay from minimum to larger values as needed for phase synchronization, resolving the contradiction between fixed minimum delay (small area) and adjustable delay (larger range).
Solution Approach 2:
The patent changes the delay parameter dynamically by using a delay amount controlling unit that receives control signals and adjusts the delay amount accordingly. This enables the delay line to vary its delay characteristic from minimum to larger values, achieving both small area (when minimum delay is sufficient) and large adjustment range (when phase synchronization requires larger delay).
2Measurement precision
If the delay amount is increased to achieve phase synchronization, then synchronization accuracy is improved, but operation failures occur when the delay amount exceeds the delay amount limit
Solution Approach 1:
The patent implements feedback control through a delay amount sensing unit that detects when the delay line reaches its delay amount limit and provides this information to the delay amount controlling unit. This feedback mechanism prevents the delay amount from exceeding the limit, ensuring reliable operation while allowing maximum useful delay for phase synchronization when needed.
Solution Approach 2:
The patent prepares for potential operation failures by implementing beforehand protection through the delay amount sensing unit that anticipates when the delay limit will be reached. This prevents excessive delay that would cause operation failures, allowing the system to safely utilize delay up to the limit for improved synchronization accuracy.
3Measurement precision
If the delay amount is dynamically adjusted, then phase synchronization is improved, but jitter increases due to excessive delay adjustment
Solution Approach 1:
The patent uses feedback from the delay amount sensing unit to control delay adjustments, ensuring that the delay amount controlling unit only makes necessary adjustments and stops when the delay limit is reached. This prevents excessive or unnecessary delay adjustments that would generate jitter, while still allowing sufficient adjustment for achieving phase synchronization precision.
Solution Approach 2:
The patent applies partial action by adjusting the delay amount only to the extent necessary for phase synchronization, rather than continuously or excessively adjusting it. The delay amount controlling unit makes precise adjustments up to the delay limit and stops, avoiding excessive adjustment that would cause jitter while achieving sufficient synchronization precision.
Data Source
AI summary
A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.