Delay Locked Loop Clock Compensation for Memory Data Synchronization
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in synchronizing data output with system clocks due to delays in clock transfer paths, leading to incomplete synchronization and potential errors in data transfer.
Innovation Solution
A semiconductor memory apparatus with a delay locked loop circuit that includes a delay line, phase comparators, and a delay controller to detect and compensate for clock delays, ensuring data is output synchronized with the system clock by generating a delay locked clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is output synchronized with the delayed system clock, then data access speed increases, but data synchronization with external devices deteriorates
Solution Approach 1:
The delay locked loop circuit performs preliminary action by intentionally delaying the system clock before it reaches the output circuit. The delay amount is precisely controlled to match the essential delay in the clock transfer path, so that when data is output synchronized with this pre-delayed clock, both high-speed access and accurate synchronization with external devices are achieved simultaneously.
2Reliability
If the delay locked loop circuit is added to compensate for clock delay, then data synchronization improves, but device complexity increases
Solution Approach 1:
The delay locked loop circuit implements feedback by continuously monitoring the phase difference between the delayed system clock and the original system clock, and automatically adjusting the delay amount to maintain optimal synchronization. This feedback mechanism ensures accurate data synchronization while using a standardized loop structure that is well-established in clock management, helping to control overall system complexity.
Data Source
AI summary
A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.