Variable Clock Divider DLL for Low-Power Phase Alignment
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Solution Overview
Problem
In synchronous DRAMs, the DLL circuit struggles to accurately synchronize the output clock signal with the external clock signal during periods of no read data output, especially due to PVT fluctuations, leading to increased current consumption and misalignment issues when the internal clock signal frequency is high or divided.
Innovation Solution
The DLL circuit employs a variable clock divider and phase detector, along with a delay adjustment circuit and replica circuit, to dynamically adjust the output clock signal frequency and phase alignment, ensuring correct synchronization regardless of the division ratio and reducing current consumption by switching between dividing and non-dividing modes based on operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal clock signal frequency is lowered to reduce current consumption, then current consumption decreases, but phase alignment accuracy deteriorates due to PVT fluctuations
Solution Approach 1:
The patent implements a variable clock divider that can dynamically switch between different division ratios (1st, 2nd, 3rd, 4th dividers) based on operational requirements. This allows the system to adaptively adjust the clock frequency to PVT fluctuations while maintaining phase alignment accuracy, resolving the contradiction between current consumption and phase alignment precision.
Solution Approach 2:
The patent changes the division ratio parameter of the clock divider based on detected phase alignment status. When PVT fluctuations cause misalignment, the system switches to a different division ratio to restore accurate phase alignment, thereby maintaining measurement precision while managing current consumption.
2Use of energy by moving object
If the DLL circuit is stopped during periods of no read data output, then current consumption decreases, but phase alignment is lost requiring periodic reactivation
Solution Approach 1:
The patent implements periodic activation of the DLL circuit at predetermined intervals even during low-activity periods. This periodic operation maintains phase alignment accuracy by continuously tracking PVT fluctuations, while still achieving significant current consumption reduction compared to continuous operation.
Solution Approach 2:
The patent uses a feedback mechanism where the phase detector continuously monitors phase alignment between internal and external clock signals. Based on this feedback, the system determines when to activate or deactivate the DLL circuit, ensuring phase alignment is maintained while minimizing current consumption.
3Use of energy by moving object
If the phase detector is placed after the clock divider, then current consumption is reduced, but phase determination fails in certain division ratio scenarios
Solution Approach 1:
The patent segments the phase detection function across multiple stages: phase detectors are placed both before and after the clock divider. The first phase detector operates at higher frequency to detect gross misalignments, while the second phase detector operates at lower frequency to verify fine alignment, together providing complete phase determination coverage.
Solution Approach 2:
The patent introduces an intermediary control mechanism that coordinates between the first and second phase detectors. This intermediary logic determines when to switch between different division ratios based on phase alignment status, ensuring accurate phase determination is maintained while minimizing current consumption.
Data Source
AI summary
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.