Delay-Locked Loop Clock Driving for High-Speed Memory Timing Margin
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Solution Overview
Problem
Conventional delay locked loops in semiconductor memory devices face limitations in operation frequency due to a narrow permissible range of delay for generating data output enable signals, leading to potential malfunctions as the frequency increases.
Innovation Solution
The proposed solution involves a delay locked loop with a first driving block generating DLL clocks for read operations and a second driving block generating DLL clocks for write operations, where the first driving block has a larger delay amount than the second, ensuring a sufficient operation margin by adjusting the delay amounts and operational delays between the blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operation frequency of the semiconductor memory device is increased, then the data transfer speed is improved, but the permissible range of delay for generating data output enable signals becomes narrower, leading to potential malfunctions
Solution Approach 1:
The driving unit is divided into a first driving block for read operations and a second driving block for write operations. Each block has independently adjustable delay amounts, allowing optimized timing for different operation types. This segmentation enables the system to maintain reliable operation at high frequencies by providing tailored delay compensation for each operation mode.
Solution Approach 2:
The delay amounts in both driving blocks are made dynamically adjustable through delay controllers that can modify the delay parameters based on operating conditions. This dynamic adjustment capability allows the system to adapt to varying frequencies and maintain optimal timing margins, preventing malfunctions as frequency increases.
2Device complexity
If a conventional delay locked loop with unified driving block is used, then the device complexity is reduced, but the operational margin at high frequencies is insufficient
Solution Approach 1:
The unified driving block is segmented into separate first and second driving blocks with different delay characteristics. The first driving block targets read operations while the second targets write operations, allowing each to be optimized independently. This segmentation increases operational margin without excessive complexity increase.
Solution Approach 2:
Each driving block is given different local characteristics - the first driving block has delay parameters optimized for read operations while the second has parameters optimized for write operations. This local quality differentiation allows each block to operate within safe timing margins for its specific function, even at high frequencies.
Data Source
AI summary
A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.