DLL Clock Duty Adjustment Using Counter-Based Delay Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing duty adjustment circuits for clock signals in synchronous memories are limited to a narrow frequency range due to varying capacitor discharge amounts, leading to saturation at low frequencies and misjudgment at high frequencies, and require oscillators that can act as noise sources.
Innovation Solution
A clock generation circuit using a delay line and counter circuit to adjust the delay and duty of clock signals, allowing for precise duty adjustment independent of clock signal frequency without oscillators, by acquiring multiple count values to adjust the position of active edges and maintaining a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical duty adjustment circuit using capacitor discharge is used, then the duty can be adjusted, but the circuit is only applicable to a narrow frequency range due to varying discharge amounts
Solution Approach 1:
The invention changes the operating parameters by using oscillators to generate clock signals with different frequencies (first frequency and second frequency) instead of relying on capacitor discharge amounts. This allows the duty adjustment circuit to operate across a wide frequency range while maintaining accurate duty detection, as the oscillator-based approach is not subject to the frequency-dependent discharge amount variations that plague capacitor-based circuits.
Solution Approach 2:
The invention uses a replica buffer to create a copy (replica clock signal) of the internal clock signal. This replica is then used by the oscillators to generate the first and second clock signals for duty adjustment. By copying the clock signal and using it to drive oscillators, the system achieves frequency-independent duty adjustment while maintaining the original clock signal integrity.
2Adaptability or versatility
If oscillators are used to adjust rise and fall edges, then the applicable frequency range is extended, but noise sources are introduced
Solution Approach 1:
The invention introduces a replica buffer as an intermediary between the internal clock signal and the oscillators. The replica buffer creates a clean copy of the clock signal that drives the oscillators, isolating the oscillators from directly processing the original clock signal. This intermediary approach allows the oscillators to operate across wide frequency ranges while minimizing their noise impact on the primary clock distribution network.
3Object-generated harmful factors
If a delay line is used without oscillators, then noise sources are eliminated, but the duty adjustment becomes frequency-dependent
Solution Approach 1:
The invention employs periodic action by using oscillators that generate clock signals at different frequencies (first frequency for rise edge, second frequency for fall edge). These periodic oscillations enable the delay line to achieve frequency-independent delay adjustment, as the oscillators provide the necessary timing references regardless of the input clock frequency, thereby extending the applicable frequency range without introducing significant noise.
Data Source
AI summary
To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount of delay of the delay line; a counter control circuit that adjusts a count value of the counter circuit; and a subtraction circuit that determines a difference between first and second count values at which the rise edge of the first internal clock signal coincides with that of a replica clock signal. The fall edge of the second internal clock signal is adjusted based on a value equivalent to one-half of the difference obtained. This prevents the applicable frequency range from being limited as with a type of duty adjustment circuit that alternately discharges capacitors.