DLL Reference Clock Duty-Cycle Compensation Under Voltage Variation
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Solution Overview
Problem
DLL circuits in semiconductor integrated circuits face reliability issues due to variable duty ratios in the reference clock generated, leading to delayed data output and potential erroneous operations when the power supply voltage changes.
Innovation Solution
An apparatus and method that involves generating a reference clock with a constant duty ratio using a buffering unit to create a first and second reference clock, inverting the second clock, and a duty cycle compensating unit to mix the phases of these clocks, ensuring the reference clock remains stable despite power supply changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock buffer is used to generate the reference clock, then the device complexity is reduced, but the duty ratio becomes variable when power supply voltage changes
Solution Approach 1:
The single clock buffer is divided into two separate clock buffers (first clock buffer and second clock buffer). Each buffer generates a reference clock signal independently, allowing the duty cycle compensating unit to selectively combine them to maintain a stable 50% duty ratio even when power supply voltage fluctuates.
Solution Approach 2:
A duty cycle compensating unit is introduced as an intermediary component between the clock buffers and the DLL circuit. This unit receives clock signals from multiple buffers, determines which signal has the correct duty ratio, and outputs the appropriate signal, thereby ensuring duty ratio stability without requiring complex circuitry in the buffers themselves.
2Reliability
If the duty ratio of the reference clock varies, then the DLL circuit operation becomes unreliable, but adding duty ratio compensation increases device complexity
Solution Approach 1:
The duty cycle compensating unit dynamically selects between multiple clock buffer outputs based on real-time duty ratio conditions. By monitoring the duty ratio of each buffer output and selectively passing through the appropriate signal, the system maintains DLL reliability without requiring complex active compensation circuitry.
Solution Approach 2:
The system changes the operational parameter approach by using multiple clock buffers with potentially different duty ratios under varying power conditions, and the duty cycle compensating unit adapts by selecting the appropriate buffer output. This parameter-based selection strategy achieves reliability without complex circuit modifications.
3Device complexity
If power supply voltage changes are allowed to affect the reference clock, then the circuit operates simpler, but data output timing becomes delayed
Solution Approach 1:
The duty cycle compensating unit performs preliminary action by pre-selecting and outputting the clock signal with the correct duty ratio before it reaches the DLL circuit. This ensures that the DLL receives a properly timed reference clock from the start, preventing any downstream timing delays that would otherwise occur due to duty ratio distortion.
Data Source
AI summary
An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.