Memory DLL Clock Mixing With Duty Cycle Correction at High Frequency
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Solution Overview
Problem
As semiconductor memory devices operate at higher frequencies, the time margin for exact delay locking of system clock signals is reduced, making it difficult for conventional DLL circuits to perform precise delay locking operations, especially for the second DLL circuit which operates with a half-clock time difference.
Innovation Solution
The semiconductor memory device incorporates a first and second clock buffer, an analog duty cycle correction circuit, a mixing circuit, and DLL circuits that perform delay locking operations on duty cycle-corrected clock signals, with dividers activating only when the frequency exceeds a predetermined value, allowing direct feedback without additional duty cycle correction, thereby stabilizing the delay-locked clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock frequency is increased to improve data input/output speed, then productivity is improved, but the time margin for delay locking is reduced making delay locking operation more difficult
Solution Approach 1:
The patent applies preliminary action by performing duty cycle correction on the system clock signal before it is input to the DLL circuit. The first and second clock buffers correct the duty cycle of the clock signal in advance, ensuring that the DLL circuit receives a pre-corrected clock signal with accurate duty cycle (50%). This preliminary correction compensates for the reduced time margin at high frequencies, allowing the DLL to perform delay locking operation accurately even when operating with compressed timing windows.
2Device complexity
If conventional DLL circuits are used without preliminary duty cycle correction, then device complexity is reduced, but manufacturing precision of delay locking is insufficient
Solution Approach 1:
The patent introduces preliminary duty cycle correction through first and second clock buffers that operate before the DLL circuit. These buffers pre-adjust the duty cycle of the system clock signal to 50% using simple buffer circuits with inverted output signals. This preliminary action ensures accurate delay locking precision without requiring complex duty cycle correction mechanisms within the DLL circuit itself, thus maintaining relatively simple device complexity while achieving high manufacturing precision.
Solution Approach 2:
The patent uses the first and second clock buffers as intermediary components between the system clock input and the DLL circuit. These buffers serve as mediators that correct the duty cycle of the clock signal before it reaches the DLL circuit, isolating the DLL from duty cycle variations. This intermediary approach allows the DLL to focus solely on delay locking operation with a pre-conditioned clock signal, improving precision without significantly increasing overall device complexity.
3Productivity
If the second DLL circuit operates with half-clock time difference to process both rising and falling edges, then productivity is improved, but the difficulty of detecting and measuring delay timing increases
Solution Approach 1:
The patent uses the first and second clock buffers as intermediary components that process the system clock signal before it reaches the DLL circuits. The first clock buffer processes the clock signal for the first DLL circuit, while the second clock buffer processes the inverted clock signal for the second DLL circuit. This intermediary processing ensures that each DLL circuit receives a clean, duty-cycle-corrected clock signal, making it easier to detect and measure delay timing even when operating with half-clock time differences for processing both rising and falling edges.
Data Source
AI summary
A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.