Duty Cycle Correction Circuit for DLL Clock Edge Alignment
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Solution Overview
Problem
In semiconductor apparatuses, precise control of the duty cycle of a clock is crucial to prevent data distortion, especially in synchronous systems like DDR, where data is input/output at both rising and falling edges, and existing methods struggle to maintain a 50:50 duty cycle effectively.
Innovation Solution
A method involving a duty cycle correction process that adjusts the phase of both the rising and falling edges of a clock using a delay locked loop and a duty cycle correction block, which generates a duty corrected clock by delaying the external clock and adjusting phases to ensure a 50:50 duty cycle, thereby compensating for clock skew and maintaining data synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a duty cycle correction method adjusting only one edge phase is used, then the device complexity is reduced, but the manufacturing precision of the duty cycle cannot be achieved
Solution Approach 1:
The duty cycle correction function is segmented into two independent correction blocks: a first duty cycle correction block that adjusts the rising edge phase, and a second duty cycle correction block that adjusts the falling edge phase. Each block operates independently to correct one edge, allowing precise duty cycle control without requiring a single complex correction mechanism.
2Loss of time
If phase adjustment is performed before DLL locking, then the duty cycle correction speed is improved, but the rising edge phase accuracy deteriorates due to subsequent DLL phase adjustments
Solution Approach 1:
The first duty cycle correction block performs preliminary adjustment of the rising edge phase before the DLL locking process. This preliminary action ensures that the rising edge is correctly positioned early in the startup sequence, and the DLL locking process is designed to maintain this positioning without causing subsequent phase drift.
Solution Approach 2:
The system implements feedback mechanisms where the duty cycle correction blocks continuously monitor and adjust the clock edges based on detected phase differences. This feedback ensures that any phase drift during DLL locking is compensated, maintaining rising edge accuracy throughout operation.
Data Source
AI summary
A semiconductor apparatus includes a duty cycle correction block and a delay locked loop. The duty cycle correction block generates a duty corrected clock by correcting a duty cycle of an internal clock, adjusts a phase of a rising edge of the duty corrected clock when a delay locked loop is reset, and adjusts a phase of a falling edge of the duty corrected clock when the delay locked loop is locked. The delay locked loop receives an external clock to output the internal clock, and delays the external clock by a variable delay amount to output the internal clock when the adjustment of the phase of the rising edge of the duty corrected clock by the duty cycle correction block is completed.