DLL Clock Duty Cycle Correction Using Frequency-Region Switching
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Solution Overview
Problem
Conventional duty cycle correcting circuits in semiconductor integrated circuits face limitations in achieving both linear control and a wide frequency range, with analog type circuits restricted by frequency range and digital type circuits struggling with linear control.
Innovation Solution
A semiconductor integrated circuit design that includes a frequency determining unit, a duty cycle control unit, and a duty cycle correcting unit, which generates a corrected clock by adjusting voltage levels based on bias currents to control the duty cycle of the DLL clock, allowing operation across a wide frequency region while maintaining linear control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an analog type duty cycle correcting circuit is used, then linear control is achieved, but the operation frequency region is limited
Solution Approach 1:
The frequency determining unit divides the operation frequency range into multiple frequency regions, and selectively activates corresponding correction circuits for each region. This segmentation allows the system to maintain linear control within each frequency region while covering a wide overall frequency range, resolving the contradiction between linear control capability and frequency region coverage.
Solution Approach 2:
The circuit dynamically switches between different correction circuits based on the detected frequency region. By making the circuit configuration adaptive and changeable according to operating conditions, the system achieves both linear control (through analog correction circuits) and wide frequency coverage (through dynamic switching to appropriate circuits for each frequency region).
2Adaptability or versatility
If a digital type duty cycle correcting circuit is used, then a wide operation frequency region is achieved, but linear control is difficult
Solution Approach 1:
The frequency determining unit divides the operation frequency range into multiple frequency regions, and selectively activates corresponding correction circuits for each region. This segmentation allows the system to maintain linear control within each frequency region while covering a wide overall frequency range, resolving the contradiction between linear control capability and frequency region coverage.
Solution Approach 2:
The patent introduces an intermediate frequency-to-digital converting unit that bridges the digital frequency detection and the analog correction circuits. This intermediary conversion mechanism enables digital type circuits to work with analog correction circuits, achieving both wide frequency coverage and linear control by translating digital frequency information into analog control signals.
3Productivity
If the operational speed of semiconductor integrated circuits increases, then processing capability is improved, but clock duty ratio stability deteriorates
Solution Approach 1:
The duty cycle control unit detects the actual duty cycle of the DLL clock and generates a duty cycle control signal based on this feedback. This feedback mechanism allows the system to continuously monitor and correct clock duty ratio distortions that occur at high operational speeds, maintaining stability even as processing capability increases.
Solution Approach 2:
The duty cycle correcting unit adjusts the duty ratio parameter of the clock signal by controlling the voltage levels at different nodes based on the frequency region and detected duty cycle. By dynamically changing the clock duty ratio parameter in response to operational conditions, the system maintains stable clock timing at higher operational speeds.
Data Source
AI summary
A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.