Delay-Locked Loop Clock Gating After Duty Ratio Compensation
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Solution Overview
Problem
Conventional delay locked loop circuits experience unnecessary power consumption after completing the duty ratio compensating operation due to the continuous enabling of the second delay locking unit, even when the second compensation unit is not operated.
Innovation Solution
Incorporating a clock control unit that disables the second internal clock and second delay locking unit after the duty ratio compensation is completed, utilizing a compensation finishing signal to prevent unnecessary toggling of the compensated external clock and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second delay locking unit remains enabled after duty ratio compensation is completed, then the circuit maintains operational readiness, but unnecessary power consumption occurs due to continuous toggling of the second internal clock
Solution Approach 1:
The patent applies dynamics by making the enable state of the second delay locking unit changeable based on operational conditions. The unit is enabled during duty ratio compensation operations and disabled after completion, allowing the system to adapt its power consumption state to current operational needs while maintaining reliability when required
Solution Approach 2:
The patent changes the operational parameter (enable/disable state) of the second delay locking unit based on the completion status of duty ratio compensation. By transitioning the unit from an enabled state during compensation to a disabled state after completion, the system optimizes power consumption while maintaining operational readiness when needed
2Use of energy by moving object
If the second delay locking unit is disabled after duty ratio compensation, then power consumption is reduced, but the circuit may not respond quickly if compensation is needed again
Solution Approach 1:
The patent implements periodic action by enabling the second delay locking unit only during specific operational phases (duty ratio compensation) and disabling it during other phases. This periodic enable/disable pattern reduces power consumption during non-critical periods while ensuring the unit is activated when compensation operations are required
3Reliability
If the compensated external clock continues to toggle after duty ratio compensation completion, then the circuit remains in a ready state, but unnecessary toggling increases power consumption
Solution Approach 1:
The patent extracts the unnecessary toggling function by disabling the second delay locking unit after duty ratio compensation completion. This removes the source of wasted energy (continuous clock toggling) while preserving the essential functionality of the circuit, as the unit can be re-enabled when compensation is needed again
Data Source
AI summary
A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.