Multiphase DLL Clock Locking with Initial Control Voltage Setting
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Solution Overview
Problem
Conventional multiphase DLL circuits face challenges in stabilizing the operation of multiphase clock signals due to long locking times and susceptibility to errors like harmonic or sub-harmonic lock, primarily because they lack a technical configuration to control the initial level of the control voltage effectively.
Innovation Solution
A DLL circuit with a delay unit that adjusts the delay amount based on control voltage levels, an initial operation control unit to set the control voltage to a reference level, and a phase detector to generate phase detection signals, enabling a charge pump to generate pumping voltage and a low pass filter to produce the control voltage, thereby preventing abnormal lock conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional multiphase DLL circuit operates without initial control voltage regulation, then the circuit structure remains simple, but the locking time becomes long and harmonic or sub-harmonic lock errors occur
Solution Approach 1:
The patent applies preliminary action by setting the initial control voltage to a predetermined level before the DLL locking process begins. The initial operation control unit pre-regulates the control voltage to ensure it starts within an optimal range, preventing harmonic or sub-harmonic lock errors from occurring in the first place, rather than correcting them after they occur.
Solution Approach 2:
The patent introduces an intermediary component - the initial operation control unit - that acts as a mediator between the voltage pumping operation and the delay line. This unit regulates the initial level of the control voltage before it reaches the delay line, ensuring stable operation and preventing locking errors without requiring complex modifications to the entire circuit.
2Reliability
If the locking time of the multiphase DLL circuit is long, then the circuit can operate without additional control mechanisms, but the clock signals are subject to harmonic or sub-harmonic lock errors
Solution Approach 1:
The patent applies preliminary action by pre-setting the control voltage to an appropriate initial level before the locking process begins. This initial voltage regulation ensures that the phase detector and charge pump operate correctly from the start, enabling the circuit to achieve accurate phase locking quickly without falling into harmonic or sub-harmonic lock states.
Solution Approach 2:
The patent implements feedback by using the phase detector to continuously monitor the phase difference between the reference clock signal and the DLL clock signal. The detection enable signal activates the charge pump based on this feedback, allowing the control voltage to be dynamically adjusted during the locking process to achieve and maintain accurate phase synchronization.
3Stability of the object's composition
If the control voltage level is not properly controlled in initial operation, then the circuit design remains simple, but the multiphase DLL clock signal cannot be stably operated
Solution Approach 1:
The patent applies preliminary action by pre-regulating the control voltage to a predetermined initial level before the DLL locking process begins. The initial operation control unit ensures that the control voltage starts within an optimal range, which is essential for stable operation of the multiphase DLL clock signal and prevents locking errors from occurring.
Solution Approach 2:
The patent introduces an intermediary component - the initial operation control unit - that acts as a mediator to regulate the control voltage. This unit is specifically designed to control the initial level of the control voltage during the startup phase, providing stable operation without requiring complex control mechanisms throughout the entire circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a DLL circuit with a shorter locking time and stable operation of multiphase clock signals by controlling the control voltage levels, preventing errors such as harmonic or sub-harmonic lock, and ensuring the control voltage remains within a predetermined range.
Implementation Method 1
a charge pump configured to generate a pumping voltage through a voltage pumping operation in response to the phase detection signal
Implementation Method 2
a low pass filter configured to generate the control voltage by filtering the pumping voltage
Data Source
AI summary
A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.