DLL-Based Multi-Phase Clock Generation for Jitter Tracking
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Solution Overview
Problem
High-speed I/O data circuits face performance issues due to general-purpose designs and packet-based communication, which result in large memory requirements and significant latency penalties, particularly in maintaining synchronization and controlling phase spacing errors in clock signals.
Innovation Solution
A multi-phase clock generator using a delay-locked loop (DLL) with a delay line and control circuit that adjusts based on rising and falling edges of output clock signals to minimize phase spacing errors and jitter, ensuring accurate phase distribution across 360 degrees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general-purpose design is used for I/O interfaces, then versatility is improved, but performance is worsened
Solution Approach 1:
The patent implements interface-specific optimization by providing separate clock generators for different interface types (e.g., USB 3.0, SATA, SAS) rather than using a single general-purpose design. Each clock generator is tuned to the specific timing requirements of its interface, achieving local optimization that improves performance while maintaining overall system versatility through modular architecture.
2Adaptability or versatility
If packet-based communication is used, then data transfer flexibility is improved, but latency is worsened
Solution Approach 1:
The patent implements preliminary synchronization by using delay-locked loops (DLL) to pre-adjust clock phase alignment before data transmission begins. This preliminary action ensures that sampling clocks are properly synchronized with data clocks in advance, eliminating latency that would otherwise occur during packet-based communication setup and maintaining high-speed data transfer efficiency.
3Measurement precision
If delay-locked loop is used for clock generation, then phase accuracy is improved, but device complexity is worsened
Solution Approach 1:
The patent segments the clock generation system into multiple independent delay-locked loops, with each DLL responsible for generating clocks for a specific interface. This segmentation isolates the complexity of DLL circuits to modular units, making the overall system more manageable while maintaining high phase accuracy for each interface through dedicated DLL optimization.
Data Source
AI summary
Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.