Delay-Locked Loop Initialization for Fast Clock Locking Range
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits face challenges in achieving quick locking states and have limited locking ranges, often resulting in unstable harmonic locking due to the phase detector's limited ability to synchronize the output clock signal with the reference clock signal.
Innovation Solution
The proposed DLL circuit includes a phase detector, a control voltage generator, and a control voltage initializer, which generates an initial control voltage based on digital codes derived from the characteristics of the voltage controlled delay line, allowing for selective input to the loop filter and enabling faster locking and increased locking range by approximating the locking control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL circuits use a phase detector and charge pump to synchronize clock signals, then the output clock signal can be synchronized with the reference clock signal, but the locking time is prolonged and the locking range is limited
Solution Approach 1:
The patent applies preliminary action by introducing a delay measuring unit that pre-measures the delay amount between reference and output clock signals before the locking process begins. This initial measurement allows the system to start with an optimized control voltage, significantly reducing the time required to achieve locking while maintaining stable synchronization. The delay measurement is performed in advance using a separate measuring path that does not interfere with the normal operation path.
Solution Approach 2:
The patent uses an intermediary approach by introducing a delay measuring unit as a separate measurement path that operates independently from the main signal path. This intermediary unit measures the actual delay characteristics and provides this information to the control voltage generator, which then adjusts the control voltage accordingly. This intermediary measurement mechanism enables faster locking without compromising the stability of the main signal path.
2Reliability
If the phase detector compares clock phases to achieve synchronization, then phase alignment can be achieved, but the locking range remains limited
Solution Approach 1:
The patent implements feedback by using the delay measuring unit to continuously monitor the actual delay amount and feed this information back to the control voltage generator. The control voltage generator adjusts the control voltage applied to the delay elements based on this feedback, enabling the system to adapt to different delay conditions and expand the locking range while maintaining accurate phase synchronization through the phase detector.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the control voltage parameter based on the measured delay amount. The control voltage generator modifies the control voltage to optimize the delay characteristics of the delay elements, allowing the system to adapt to varying conditions and expand the locking range while maintaining reliable phase synchronization.
3Measurement precision
If multiple delay elements are used to achieve precise delay control, then the delay accuracy is improved, but the circuit complexity increases
Solution Approach 1:
The patent applies self-service by introducing a delay measuring unit that automatically measures the delay characteristics and provides this information to the control voltage generator. This self-measuring and self-adjusting mechanism eliminates the need for complex manual calibration or external testing equipment, achieving high delay accuracy through automated feedback while keeping the overall system design relatively simple and self-contained.
Data Source
AI summary
A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.