DLL Clock Generator Using Nested Delay Lines for Low Phase Noise
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Solution Overview
Problem
Conventional clock generators, such as PLL and DLL, face issues with increased phase noise and hardware complexity, especially when generating multiple frequencies, with DLL clock generators requiring a large number of transistors to achieve frequency multiplication.
Innovation Solution
A DLL clock generator configuration that includes a first crystal oscillator, a delay locked loop with a frequency multiply function, a frequency divider, and a second crystal oscillator, along with a phase frequency detector, allowing for the generation of various frequency clock signals without increasing hardware complexity by using programmable values for frequency multiplication and division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency multiplier is included in the DLL clock generator to output a clock signal having a frequency that is N/2 times that of the input clock signal, then the frequency multiplication capability is improved, but the number of transistors increases in proportion to N
Solution Approach 1:
The frequency multiplication function is segmented into multiple stages: a first voltage controlled delay line with N delay cells performs initial frequency multiplication, and a second voltage controlled delay line with M delay cells performs further multiplication. This segmentation allows the total multiplication factor to be achieved with fewer transistors than a single-stage approach, as each stage operates with a manageable number of cells.
Solution Approach 2:
The patent implements nested frequency multiplication by using the output of the first voltage controlled delay line as the input to the second voltage controlled delay line. The first delay line multiplies the input frequency by N/2, and the second delay line further multiplies this intermediate frequency by M/2, achieving a total multiplication of NM/4 times the original frequency with reduced hardware complexity.
2Speed
If N delay cells are required to obtain a frequency of N/2-tuple in the conventional DLL clock generator, then the frequency multiplication is achieved, but the complexity of the frequency divider increases in proportion to N
Solution Approach 1:
The frequency division operation is segmented into two separate dividers: a first frequency divider that divides by N and a second frequency divider that divides by M. This segmentation reduces the complexity of each individual divider compared to a single divider handling the full NM division, as divider complexity increases logarithmically with the division ratio.
Solution Approach 2:
The patent employs programmable delay lines with controllable numbers of delay cells (N and M) that can be dynamically adjusted. This dynamic configuration allows the system to adapt the frequency multiplication and division ratios as needed, optimizing the balance between frequency range and hardware complexity for different operating conditions.
3Adaptability or versatility
If a voltage controlled oscillator is used in the PLL clock generator to change frequency according to phase difference, then frequency adjustment capability is improved, but phase noise increases due to positive feedback circuit
Solution Approach 1:
The patent extracts and removes the voltage controlled oscillator from the clock generation system, replacing it with voltage controlled delay lines that adjust signal delay rather than frequency oscillation. This extraction eliminates the positive feedback circuit inherent in VCOs, thereby reducing phase noise while maintaining frequency adjustment capability through delay-based frequency multiplication.
Solution Approach 2:
The patent substitutes the electrical oscillation mechanism of the VCO with a delay-based frequency multiplication mechanism. Instead of using a voltage controlled oscillator that generates frequency through positive feedback, the system uses delay locked loops where frequency multiplication is achieved by cascading delay cells, replacing the oscillatory mechanism with a delay-based approach that has lower phase noise.
Data Source
AI summary
Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.