DLL Clock Mixing Control for Low-Jitter Frequency Adaptation
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Solution Overview
Problem
Existing semiconductor devices face performance issues when the frequencies of the source clocks applied to them differ from the frequencies determined during design, leading to jitter and prolonged synchronization times in DLL circuits.
Innovation Solution
A semiconductor device with a reset signal generator and mixing control signal generators that adjust the number and activation status of reset signals based on external clock frequencies, allowing the DLL circuit to dynamically adjust the delay amount and driver power for optimal performance across varying frequency conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the DLL circuit uses fixed delay amount and driver power determined during design, then the circuit structure is simple, but the performance deteriorates when source clock frequencies deviate from design frequencies
Solution Approach 1:
The patent implements dynamic adjustment of delay amounts and driver powers based on detected source clock frequency. The delay control signal and driver control signal are varied according to frequency conditions, allowing the DLL circuit to adapt to different operating frequencies rather than relying on fixed design-time parameters. This resolves the contradiction by making the circuit performance reliable across frequency variations without substantially increasing structural complexity.
Solution Approach 2:
The patent changes operational parameters (delay amount, driver power) based on source clock frequency detection. By adjusting these parameters dynamically according to the actual frequency conditions, the circuit maintains optimal synchronization performance whether the source clock frequency is higher or lower than the design frequency, without requiring a completely different circuit architecture.
2Device complexity
If the DLL circuit uses fixed delay amount determined during design, then the device complexity is low, but the synchronization time increases when frequencies differ from design values
Solution Approach 1:
The patent dynamically adjusts the delay amount based on the detected source clock frequency. When the frequency deviates from the design value, the delay control signal is modified to compensate, enabling faster synchronization without adding complex hardware structures. This resolves the contradiction by making synchronization time adaptive rather than fixed.
Solution Approach 2:
The patent incorporates frequency detection and uses the detected frequency information to adjust the delay amount dynamically. This feedback mechanism allows the circuit to automatically compensate for frequency deviations, reducing synchronization time without requiring complex pre-configured structures for every possible frequency condition.
3Adaptability or versatility
If the DLL circuit operates with source clock frequencies different from design frequencies, then the adaptability increases, but jitter increases and performance deteriorates
Solution Approach 1:
The patent adjusts driver power based on the detected source clock frequency to maintain optimal signal quality across different operating conditions. By dynamically changing the driver control signal according to frequency variations, the circuit maintains low jitter and high signal integrity whether operating above or below the design frequency, thus preserving reliability while achieving frequency adaptability.
Solution Approach 2:
The patent implements dynamic control of driver power in response to frequency variations. This allows the circuit to maintain consistent signal quality and low jitter across different frequency conditions by adapting the driving strength appropriately, resolving the contradiction between frequency adaptability and signal quality maintenance.
Data Source
AI summary
A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.