DLL Clock Generator for Non-Harmonic Frequency Translation
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Solution Overview
Problem
Current clock generator designs face challenges in creating a non-harmonic relationship between input and output clocks, particularly in multi-radio combo-chip products, where harmonic interference and frequency planning complexities lead to increased area and current consumption due to the need for analog blocks like frequency dividers and mixers.
Innovation Solution
A clock generator utilizing a delay locked loop (DLL) and edge rotator to generate multiple phases of a clock signal, allowing for non-harmonic frequency translation and autonomous calibration to compensate for phase errors, thereby avoiding harmonic interference and simplifying frequency planning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional analog blocks (frequency dividers and mixers) are used to generate non-harmonic clock relationships, then the frequency offset ratio is limited to rational numbers and LC-tank is required for side-band spur suppression, but this increases circuit area and current consumption
Solution Approach 1:
The patent replaces the mechanical/analog approach (LC-tank oscillators with analog frequency dividers and mixers) with a digital approach. The digital phase-locked loop (DPLL) uses digital frequency dividers, digital mixers, and digital signal processing to generate non-harmonic clock relationships. This substitution eliminates the need for large-area LC-tanks and reduces current consumption while maintaining frequency flexibility through digital control mechanisms.
Solution Approach 2:
The patent changes the operating parameters from analog continuous-domain signals to digital discrete-domain signals. By using digital frequency dividers with programmable division ratios and digital mixers with programmable frequency offsets, the system achieves flexible non-harmonic clock generation. The parameter changes include transitioning from fixed analog frequency relationships to programmable digital frequency relationships, enabling rational and irrational number frequency offsets without requiring large analog filtering components.
2Adaptability or versatility
If multiple RF oscillators are integrated in a multi-radio combo-chip, then more communication protocols are supported, but injection pulling among oscillators and harmonic interference occur
Solution Approach 1:
The patent introduces a digital frequency synthesizer as an intermediary between the reference clock and the RF oscillators. This digital synthesizer generates intermediate clock signals with precisely controlled frequencies and phases that are non-harmonically related to the reference clock. By using this intermediary digital signal generation stage, the system can provide frequency isolation between multiple RF oscillators, preventing injection pulling and harmonic interference while supporting multiple communication protocols.
Solution Approach 2:
The patent employs feedback mechanisms in the digital phase-locked loop (DPLL) to maintain precise frequency and phase relationships. The feedback loop continuously monitors the output frequency and adjusts the control parameters to compensate for drift and interference. This feedback control ensures that multiple RF oscillators operate at stable, isolated frequencies, preventing injection pulling effects while enabling multi-protocol support through programmable frequency settings.
3Ease of operation
If analog frequency division and mixing are used to generate non-harmonic clocks, then frequency translation is achieved, but the frequency offset ratio is limited to rational numbers and unwanted side-band spurs must be suppressed
Solution Approach 1:
The patent substitutes analog frequency multiplication and filtering with digital frequency synthesis techniques. Instead of using analog mixers that generate unwanted side-band spurs requiring LC-tank filtering, the system uses digital mixers and digital signal processing to generate the desired frequency offsets. The digital approach naturally suppresses spurs through precise timing and filtering in the digital domain, eliminating the need for large analog filtering components while maintaining frequency translation capability.
Data Source
AI summary
A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.