DLL Clock Circuit Mode Switching for Lower ODT Power

Solution Overview

Problem

The power consumption of DLL circuits in semiconductor devices increases with stricter phase control, and suspending these circuits is not practical due to the time required to reestablish precise phase control, especially during ODT operations where less precise timing control is needed.

Innovation Solution

Implementing a clock generating circuit with two operation modes: a precise phase control mode for read operations and a low power consumption mode for ODT operations, where the fine delay lines are suspended and only the coarse delay lines are used, reducing power consumption during ODT operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the DLL circuit operates in precise phase control mode, then the phase control precision of internal clock is improved, but power consumption increases

Engineering Contradiction:

Improvephase control precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements a dynamic operation mode switching mechanism that transitions the clock generating circuit between first mode (precise phase control) and second mode (low power consumption) based on operational requirements. The control circuit dynamically selects appropriate delay lines and adjusts circuit operation states according to whether ODT operations are needed, optimizing the balance between phase control precision and power consumption in real-time

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies different levels of phase control precision to different operational contexts. During ODT operations, only coarse delay lines are activated providing sufficient but not excessive precision, while during read operations both coarse and fine delay lines are used for high precision. This local differentiation of quality matches the actual requirements of different functional modes

Inventive Principle:

Principle #3Local quality

2Use of energy by moving object

If the DLL circuit is suspended to reduce power consumption, then power consumption is reduced, but the time to reestablish precise phase control increases

Engineering Contradiction:

Improvepower consumptionVSAvoidtime to reestablish phase control

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent maintains the clock generating circuit in an active standby state during ODT operations rather than fully suspending it. The coarse delay lines remain operational and the circuit structure is preserved, so when transitioning back to read operations, only the fine delay lines need to be activated and phase adjustment performed, rather than rebuilding the entire phase control system from scratch

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a dynamic operation mode switching mechanism that transitions the clock generating circuit between first mode (precise phase control) and second mode (low power consumption) based on operational requirements. The control circuit dynamically selects appropriate delay lines and adjusts circuit operation states according to whether ODT operations are needed, optimizing the balance between phase control precision and power consumption in real-time

Inventive Principle:

Principle #15Dynamics

3Measurement precision

If the DLL circuit operates in precise phase control mode continuously, then read data timing precision is maintained, but power consumption increases during ODT operations

Engineering Contradiction:

Improveread data timing precisionVSAvoidpower consumption during ODT

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies different levels of phase control precision to different operational contexts. During ODT operations, only coarse delay lines are activated providing sufficient but not excessive precision, while during read operations both coarse and fine delay lines are used for high precision. This local differentiation of quality matches the actual requirements of different functional modes

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies partial phase control action during ODT operations by activating only the coarse delay lines rather than the full precision control mechanism. This partial action provides sufficient timing control for ODT requirements while avoiding the excessive power consumption that would result from activating the complete precise phase control system

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8713331B2Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit

Publication Date: 2014.04.29 LONGITUDE LICENSING LTD

AI summary

A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.