DLL Clock Circuit Mode Switching for Low-Power ODT Timing
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Solution Overview
Problem
Semiconductor devices with DLL circuits face increased power consumption due to precise phase control requirements, which is not feasible for operations that do not need strict phase control, such as ODT operations, and the DLL circuit's power consumption remains high even when not in use due to long reactivation times.
Innovation Solution
A clock generating circuit with two modes: a precise phase control mode for read operations and a low power consumption mode for ODT operations, where the fine delay lines are suspended and only the coarse delay lines are used, reducing power consumption during ODT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL circuit performs precise phase control for read operations, then the phase control precision is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the delay line configuration adjustable between two states: a fine delay line configuration for precise phase control during read operations, and a coarse delay line configuration for lower power consumption during ODT operations. The selector circuit dynamically switches between these configurations based on operation mode, allowing the system to adapt its phase control precision to match the actual operational requirements.
Solution Approach 2:
The patent implements local quality by providing different delay line configurations for different operational contexts. The fine delay line provides high-resolution phase control specifically when needed for read operations, while the coarse delay line provides sufficient phase control at lower power consumption for ODT operations. This allows each part of the phase control mechanism to be optimized for its specific operational context.
2Use of energy by moving object
If the DLL circuit is suspended to reduce power consumption, then the power consumption is reduced, but the reactivation time increases
Solution Approach 1:
The patent applies preliminary action by maintaining the DLL circuit in a partially active state during ODT operations. Instead of fully suspending the DLL circuit, the coarse delay line remains operational and ready, performing preliminary phase adjustment work that can be quickly refined if needed. This prevents the DLL circuit from completely losing its phase control capability, thereby reducing reactivation time while still achieving power savings compared to full operation.
3Measurement precision
If the fine delay lines are used for ODT operations, then the phase control precision is improved, but the power consumption increases
Solution Approach 1:
The patent applies partial action by using only the coarse delay line for ODT operations, which provides sufficient phase control precision for this specific application without the excessive power consumption of the fine delay line. The fine delay line is activated only when high-precision phase control is actually required, such as during read operations, avoiding unnecessary energy expenditure for ODT operations where such precision is not needed.
Data Source
AI summary
A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.