DLL Clock Output Control for Low-Power Synchronous Memory
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Solution Overview
Problem
Conventional synchronous memory devices experience errors and high current consumption due to delays in data output synchronization, particularly during high-frequency operations, as they continuously operate even when the DLL clock is not in use.
Innovation Solution
A data output control circuit that includes a DLL circuit and a delay detection unit to generate a DLL clock by delaying an internal clock, with a sense signal controlling the DLL clock output operation, allowing the circuit to stop or adjust the DLL clock output based on phase comparison and set time intervals, thereby reducing current consumption and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit continuously operates to maintain synchronization, then the phase synchronization between reference clock and feedback clock is maintained, but current consumption increases unnecessarily when the DLL clock is not in use
Solution Approach 1:
The patent applies dynamics by making the DLL circuit operational state adjustable rather than fixed. The delay detection unit dynamically detects whether delay is actually needed by comparing set time interval with actual delay time interval, and the DLL circuit transitions between operating and non-operating states based on this detection, optimizing energy consumption while maintaining synchronization only when necessary
Solution Approach 2:
The delay detection unit enables the system to self-determine whether the DLL circuit should operate. By automatically detecting the actual delay time interval and comparing it with the set time interval, the system self-regulates the DLL circuit operation without external intervention, turning off the DLL circuit when delay is already sufficient and reducing unnecessary current consumption
2Speed
If the DLL circuit operates at high frequency to increase operating speed, then data output speed is improved, but errors occur due to reduced valid data window from delay
Solution Approach 1:
The patent implements feedback through the delay detection unit that continuously monitors the actual delay time interval and compares it with the set time interval. This feedback mechanism allows the system to detect when the DLL circuit has created excessive delay that would cause errors, and adjust or stop DLL operation accordingly, preventing data output errors while maintaining high-speed operation when appropriate
Solution Approach 2:
The system performs preliminary detection of the actual delay time interval before data output operations occur. The delay detection unit proactively measures whether the delay introduced by the DLL circuit is within acceptable limits, preventing errors before they occur by identifying problematic delay conditions in advance
Data Source
AI summary
A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.