DLL Clock Path Calibration for PVT Delay Mismatch
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Solution Overview
Problem
In semiconductor memory devices, a delay difference between the internal clock signal and the external clock signal can lead to deteriorated high-frequency performance, as the internal clock signal may be delayed more than the external clock signal, causing elongated data output times. This is exacerbated by variations in Process, Voltage, and Temperature (PVT), affecting the synchronization between the clock signal and the data strobe signal.
Innovation Solution
A delay control device and method that includes a delay locked loop (DLL) to adjust the delay time of a delay line and compensate for the delay time difference between a replica delay circuit and a real clock path delay circuit using a calibration signal, generated based on the comparison of reference and feedback clock signals, thereby synchronizing the clock and data strobe signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay locked loop (DLL) is used to synchronize internal clock signal with external clock signal, then the phase synchronization is improved, but the delay difference between replica delay circuit and real clock path delay circuit causes deterioration of high-frequency performance
Solution Approach 1:
The patent applies preliminary action by generating a calibration signal in advance that compensates for the delay difference between the replica delay circuit and the real clock path delay circuit. This calibration signal is produced before the actual clock operation, allowing the system to pre-correct for PVT-induced delay variations. The calibration signal generator creates a compensation value based on the expected delay mismatch, which is then applied to adjust the DLL output, thereby preventing high-frequency performance deterioration before it occurs.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the delay time of the delay line based on the calibration signal. The calibration signal modifies the delay parameters of the DLL to compensate for the difference between replica and real clock path delays. This parameter adjustment allows the system to adapt to PVT variations and maintain accurate phase synchronization while preventing elongation of data output access time.
2Ease of operation
If the replica delay circuit is used to control delay of the delay loop, then the delay control is simplified, but the delay time difference between replica delay circuit and real clock path delay circuit deteriorates synchronization under PVT conditions
Solution Approach 1:
The patent implements feedback by using the calibration signal to continuously compensate for the delay difference between the replica delay circuit and the real clock path delay circuit. The calibration signal generator monitors the delay mismatch and provides corrective feedback to adjust the DLL output. This feedback mechanism ensures that even though the replica delay circuit provides simple delay control, the synchronization reliability under PVT conditions is maintained by actively correcting for the inherent delay differences.
3Measurement precision
If the internal clock signal is delayed more than external clock signal, then the phase matching is achieved, but the high-frequency performance deteriorates due to elongated data output time
Solution Approach 1:
The patent applies preliminary action by pre-generating the calibration signal that compensates for delay differences before the actual high-frequency operation. This calibration is performed in advance to establish the correct phase relationship without introducing excessive delay. By preparing the compensation in advance, the system achieves accurate phase matching while maintaining the speed required for high-frequency performance and avoiding elongation of data output access time.
Data Source
AI summary
A delay control device and method are disclosed, which relate to a technology for compensating for a delay difference of a delay locked loop (DLL). The delay control device may include a delay locked loop (DLL) configured to adjust a delay time of a delay line, and compensate for a delay time of a replica delay circuit based on a calibration signal. The delay control device may include a real clock path delay circuit configured to delay an output of the delay locked loop (DLL. The delay control device may include a control signal generator configured to generate the calibration signal in consideration of a difference between the delay time of the replica delay circuit and the delay time of the real clock path delay circuit.