Delay-Locked Loop Clock Path Switching for Faster Locking
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Solution Overview
Problem
Delay locked loop circuits face prolonged locking times when the input clock signal has a duty ratio not equal to 50%, leading to delayed output clock signal generation, which can exceed one clock cycle of the input signal.
Innovation Solution
The proposed solution involves a delay locked loop circuit with a selector circuit to generate internal clock signals, delay circuits to adjust these signals, and a phase detection and delay control circuit to rapidly align the feedback clock signal with the input clock signal, utilizing multiple selection signals and phase detectors to adjust the code value for optimal delay alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional delay locked loop circuit uses a single reference clock signal path, then the circuit structure remains simple, but the locking time becomes prolonged (exceeding one clock cycle) when the input clock signal has a duty ratio not equal to 50%
Solution Approach 1:
The patent segments the reference clock signal path into two separate paths: a first reference clock signal path and a second reference clock signal path. Each path is configured to operate optimally for different duty ratio conditions. This segmentation allows the circuit to reduce locking time by selecting the appropriate path based on the input clock duty ratio, while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent implements dynamic switching between the first and second reference clock signal paths based on the duty ratio of the input clock signal. A duty ratio detection circuit dynamically determines which path to activate, allowing the circuit to adapt its structure in real-time to match operating conditions, thereby reducing locking time without permanently increasing overall circuit complexity
2Adaptability or versatility
If the delay locked loop circuit uses a single reference clock signal path optimized for 50% duty ratio, then the circuit design remains straightforward, but the locking time exceeds one clock cycle when handling non-50% duty ratio signals
Solution Approach 1:
The patent creates a universal reference clock signal system with two paths that can handle both 50% and non-50% duty ratio conditions. The first path is optimized for 50% duty ratio while the second path handles non-50% duty ratios. This multi-functional design ensures the circuit maintains fast locking performance across different duty ratio conditions while preserving straightforward design principles for each individual path
3Productivity
If the delay locked loop circuit implements rapid phase alignment for non-50% duty ratio signals, then the locking time is reduced, but the circuit complexity increases due to additional paths and control logic
Solution Approach 1:
The patent applies local quality by optimizing each reference clock signal path for specific duty ratio conditions. The first path is locally optimized for 50% duty ratio signals while the second path is locally optimized for non-50% duty ratio signals. This localized optimization allows rapid phase alignment for each condition type without requiring a completely complex unified design, as each path remains relatively simple for its intended purpose
Data Source
AI summary
A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.