DLL Clock Adjustment Circuit for Low-Power Phase Alignment
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Solution Overview
Problem
Existing semiconductor devices, such as DRAMs, face challenges in efficiently controlling the phase relationship between internal and external clock signals, leading to suboptimal performance and increased power consumption due to intermittent phase adjustment operations.
Innovation Solution
A clock adjustment circuit, including a DLL circuit with a phase comparator and timing generator, is used to control the phase relationship between clock signals by asserting a control signal cyclically, allowing for intermittent operation based on phase differences and operation environment conditions, thereby reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If phase adjustment operation is performed intermittently, then power consumption is reduced, but phase alignment accuracy may deteriorate
Solution Approach 1:
The DLL circuit dynamically adjusts its operation mode between intermittent and continuous based on phase difference conditions. When phase difference exceeds a threshold, the circuit performs continuous phase adjustment; when phase difference is within threshold, it switches to intermittent mode. This dynamic adaptation resolves the contradiction by optimizing both power consumption and phase alignment accuracy according to real-time conditions.
Solution Approach 2:
The phase comparator continuously monitors the phase difference between internal and external clock signals and provides feedback to control the timing generator. This feedback mechanism ensures that phase adjustment operations are triggered only when necessary, maintaining phase alignment accuracy while minimizing unnecessary operations that would increase power consumption.
2Measurement precision
If phase adjustment operation is performed continuously, then phase alignment accuracy is maintained, but power consumption increases
Solution Approach 1:
The timing generator implements periodic phase adjustment operations based on detected phase difference conditions. Instead of continuous operation, the circuit performs phase adjustment periodically only when phase difference exceeds the threshold, thereby maintaining phase alignment accuracy while significantly reducing power consumption during normal operating conditions.
Solution Approach 2:
The DLL circuit autonomously determines when phase adjustment is needed based on its own internal phase difference detection, eliminating the need for external mode-register-set commands. The circuit self-regulates between intermittent and continuous operation modes, optimizing power consumption while maintaining accuracy requirements.
3Loss of energy
If intermittent phase adjustment is used, then power consumption is reduced, but response time to phase changes increases
Solution Approach 1:
The circuit dynamically switches between intermittent and continuous operation modes based on phase difference thresholds. When phase difference exceeds the threshold, the circuit immediately transitions to continuous adjustment mode, ensuring rapid response to significant phase changes while maintaining low power consumption during stable conditions.
Data Source
AI summary
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.