Delay-Locked Loop Clock Alignment for DRAM Phase Offset Compensation
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Solution Overview
Problem
In Dynamic Random Access Memory (DRAM), phase deviations between target clock signals generated by the delay locked loop (DLL) can occur due to mismatches or performance deviations of devices, leading to reduced data sampling effectiveness.
Innovation Solution
The implementation of a DLL comprising a preprocessing module, a first regulable delay line, a second regulable delay line, and a first regulation module, which regulates the delay of the second synchronization clock signal based on the first target clock signal to maintain a preset phase difference between the target clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay locked loop (DLL) is used to perform phase synchronization on four-phase clock signals, then phase lock is achieved, but phase offset occurs due to device mismatches or performance deviations
Solution Approach 1:
The patent implements a feedback mechanism by comparing the phase difference between target clock signals and synchronization clock signals, then using this comparison result to regulate the delay of delay lines. This closed-loop feedback system dynamically compensates for phase offsets caused by device mismatches, thereby improving phase synchronization accuracy while maintaining manufacturing tolerances.
Solution Approach 2:
The patent changes the delay parameter of delay lines based on the detected phase difference. By dynamically adjusting the delay parameter according to the comparison result between target and synchronization clock signals, the system compensates for phase offsets without requiring precise manufacturing, thus resolving the contradiction between reliability and manufacturing precision.
2Manufacturing precision
If device mismatches are reduced to eliminate phase offset, then phase difference accuracy improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces synchronization clock signals as an intermediary reference. Instead of directly reducing device mismatches, the system uses these intermediary signals to detect phase differences and regulate delay lines accordingly. This approach achieves high phase difference accuracy without requiring complex device matching, thereby avoiding increased device complexity.
3Reliability
If phase offset is compensated through additional regulation mechanisms, then data sampling effect improves, but device complexity increases
Solution Approach 1:
The patent designs the regulation module to perform multiple functions: it compares phase differences between clock signals, determines regulation directions, and controls delay line adjustments. By making this single module multi-functional, the system improves data sampling effectiveness without proportionally increasing device complexity, as the same module handles multiple tasks in the phase compensation process.
Data Source
AI summary
A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.