DLL Non-Overlapping Clock Generation for Precise Phase Delay
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Solution Overview
Problem
Conventional non-overlapping clock generator circuits struggle to maintain precise non-overlap time and clock phase delay at high switching-capacitor integrator sampling frequencies, leading to increased current consumption and error in switched capacitor integrator circuits due to process, voltage, and temperature variations.
Innovation Solution
A non-overlapping clock generation circuit incorporating a delay lock loop (DLL) circuit that generates a control voltage to maintain precise timing, using voltage-controlled delay cells to produce clock signals with non-overlap time independent of manufacturing process variations, ensuring consistent performance across desired frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inverter delays are used to implement non-overlap time and clock phase delay time, then the circuit implementation is simple, but the timing precision deteriorates due to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a delay-locked loop (DLL) that uses feedback to continuously monitor and adjust the delay time. The loop comparator detects the phase difference between input and output clock signals, and the charge pump adjusts the delay element's delay time accordingly, ensuring precise timing control despite PVT variations
Solution Approach 2:
The patent changes the delay time parameter dynamically by adjusting the control voltage applied to the delay element. This allows the delay time to be tuned and optimized for different operating conditions, achieving precise timing control that is independent of process, voltage, and temperature variations
2Measurement precision
If non-overlap time is increased to satisfy fast corner conditions, then timing precision is improved, but current consumption increases due to extended active time requirements
Solution Approach 1:
The patent makes the non-overlap time dynamic by using a voltage-controlled delay element that can adjust its delay time based on operating conditions. This allows the circuit to use minimal non-overlap time under normal conditions, reducing current consumption, while still meeting timing requirements under extreme PVT variations
3Productivity
If sampling frequency is increased to improve productivity, then conversion speed is improved, but timing control becomes more difficult due to reduced clock period
Solution Approach 1:
The patent replaces traditional mechanical or fixed-delay timing control mechanisms with a voltage-controlled delay element that uses electrical fields to control timing. This electronic control mechanism can respond much faster and with greater precision, enabling accurate timing control even at high sampling frequencies where the clock period is very short
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise non-overlap time and clock phase delay, reducing current consumption and error in switched capacitor integrator circuits, even at high frequencies, by stabilizing the timing relationship of delayed clock signals and adjusting time delays effectively.
Implementation Method 1
a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals
Implementation Method 2
the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations
Data Source
AI summary
Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.