DLL Clock Phase Selection and Inversion for Low-Jitter Sampling
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Solution Overview
Problem
Mixed-signal integrated circuits require flexible generation of clock signals with low jitter for both analog and digital components, where the second clock signal needs to be synchronized with a reference clock and have the option to be inverted relative to the first clock signal to avoid sampling transients during transition phases.
Innovation Solution
A clock signal generator using a delay-locked loop to produce multiple delayed clock phases, with a control unit and multiplexer to select and invert the clock signals based on control words, allowing for phase shifting and inversion of the second clock signal relative to the first clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single clock signal generator is used for both analog and digital components, then circuit area and power consumption are reduced, but flexibility in clock signal generation and ability to avoid sampling transients deteriorates
Solution Approach 1:
The delay-locked loop is segmented into multiple parallel delay paths, each producing a different clock phase. A multiplexer selects among these phases to generate the second clock signal, enabling flexible phase selection while using a single integrated clock generator circuit.
Solution Approach 2:
The system dynamically selects different clock phases from the delay-locked loop based on control words and clock-invert signals. This dynamic phase selection allows the second clock signal to be adjusted relative to the first clock signal, providing flexibility to avoid sampling transients during transition phases.
2Reliability
If the second clock signal is synchronized with the reference clock signal, then digital circuit operation is ensured, but the ability to selectively invert the clock signal deteriorates
Solution Approach 1:
The system maintains synchronization with the reference clock through the delay-locked loop while dynamically allowing inversion of the second clock signal relative to the first clock signal through control words and multiplexer selection, achieving both reliability and adaptability.
Solution Approach 2:
The phase relationship between the first and second clock signals is changed as a controllable parameter. By adjusting the control word and clock-invert signal, the phase difference can be modified to achieve either synchronization or inversion as needed.
3Adaptability or versatility
If multiple clock phases are generated with even distribution, then phase flexibility is improved, but delay-locked loop complexity increases
Solution Approach 1:
The delay-locked loop is divided into multiple identical delay stages connected in parallel, each contributing to a different clock phase. This segmentation provides phase flexibility while keeping each individual stage relatively simple and regular.
Data Source
AI summary
A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.