DLL Clock Control for Timing Mismatch Across Memory Power Modes
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Solution Overview
Problem
Conventional semiconductor memory devices experience timing mismatch issues between the DLL clock before and after specific modes like power down or self refresh, leading to potential failures due to unstable power supply conditions.
Innovation Solution
A semiconductor memory device with a mode control circuit, division circuit, oscillation circuit, and control circuit that periodically activates the DLL circuit during specific modes to synchronize and lock the DLL clock, ensuring consistent timing across mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the DLL circuit is turned off during specific modes to save power, then power consumption is reduced, but timing mismatch occurs between DLL clocks before and after the mode
Solution Approach 1:
The DLL circuit is periodically turned on during specific modes at predetermined timings before and after the mode, rather than remaining continuously off. This periodic activation maintains clock timing accuracy while still reducing power consumption compared to continuous operation.
Solution Approach 2:
The DLL circuit is activated in advance at a predetermined timing before the specific mode starts and remains active for a predetermined time after the mode ends. This preliminary action ensures that the DLL clock timing is maintained and synchronized, preventing timing mismatch between modes.
2Reliability
If the DLL circuit remains continuously on to maintain timing accuracy, then timing mismatch is prevented, but power consumption increases
Solution Approach 1:
Instead of continuous operation, the DLL circuit operates periodically by being activated at specific predetermined timings before and after the specific mode. This reduces overall power consumption while maintaining timing accuracy when needed.
Solution Approach 2:
The DLL circuit's operation state is dynamically adjusted based on the specific mode timing. It is turned on at predetermined times before and after the mode, and can be turned off during the mode, adapting its operation to minimize power consumption while ensuring timing accuracy is maintained.
Data Source
AI summary
A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.